CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 25

IC CODEC STEREO AUDIO 48-LQFP

CS42325-CQZ

Manufacturer Part Number
CS42325-CQZ
Description
IC CODEC STEREO AUDIO 48-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42325-CQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
95 / 100
Voltage - Supply, Analog
3.13 V ~ 3.47 V
Voltage - Supply, Digital
3.13 V ~ 3.47 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Number Of Dac Outputs
2
Conversion Rate
96 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Number Of Channels
1 ADC/2 DAC
Supply Current
10 mA to 24 mA
Thd Plus Noise
- 88 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42325-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42325-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS838A2
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT
Inputs: Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VLC; C
Notes:
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Transition Time from CCLK to CDOUT Valid
Time from CS rising to CDOUT High-Z
21. t
22. Data must be held for sufficient time to bridge the transition time of CCLK.
23. For F
24. CDOUT should not be sampled during this time.
spi
only needed before first falling edge of CS after RST rising edge. t
SCK
CDOUT
CCLK
< 1 MHz.
CDIN
RST
CS
(Note 21)
Parameter
(Note 23)
(Note 23)
(Note 22)
t srs
t spi
Figure 6. Software Mode Timing - SPI Mode
t r2
t css
(Note 24)
t scdov
t scl
t f2
t dsu t
t sch
dh
L
t scdov
= 20 pF.
Symbol
f
t
t
t
t
t
t
t
t
sclk
dsu
csh
css
sch
t
t
t
t
srs
spi
scl
dh
r2
f2
r2
f2
spi
t cscdo
= 0 at all other times.
t csh
Min
500
500
1.0
20
66
66
40
15
-
-
-
-
-
Hi-Impedance
Max
100
100
100
100
6
-
-
-
-
-
-
-
-
CS42325
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
25

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