UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 20

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
Note
1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode.
8.2
The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level
pin. In Table 10, the encoding of the pins MODE[2:0] is given.
Table 10 Static mode basic applications
Notes
1. In column mode selection pins means:
2. In column clock means:
2003 Apr 10
MODE
Stereo audio codec with SPDIF interface
30, 31
10
11
0
1
2
3
4
5
6
7
8
9
PIN
L: pin at 0 V; M: pin at half V
xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL.
44
Static mode basic applications
MODE2
MODE SELECTION PINS
SFOR1, SFOR0
MUTE
H
H
H
H
H
H
L
L
L
L
L
L
STATIC MODE
SYMBOL
MODE1
H
H
H
H
H
H
L
L
L
L
L
L
MODE0
DDD
M
M
M
M
H
H
H
H
L
L
L
L
; H: pin at V
HIGH, HIGH
(1)
LOW, HIGH
HIGH, LOW
LOW, LOW
LEVEL
HIGH
LOW
INPUT
SPDIF
PLL
PLL
PLL
PLL
PLL
−
−
−
−
−
−
DDD
.
set I
set LSB-justified 16 bits format for digital data input interface and
MSB-justified format for digital data output interface
set LSB-justified 24 bits format for digital data input interface and
MSB-justified format for digital data output interface
set MSB-justified format for digital data input and output interface
normal operation
mute active
OUTPUT
SPDIF
PLL
PLL
PLL
PLL
xtal
xtal
xtal
xtal
xtal
xtal
xtal
2
S-bus format for digital data input and output interface
20
ADC
xtal
xtal
xtal
xtal
xtal
xtal
−
−
−
−
−
CLOCK
not used
DAC
PLL
PLL
PLL
PLL
PLL
PLL
PLL
xtal
xtal
xtal
(2)
DESCRIPTION
−
I
2
SLAVE
INPUT
S-BUS
PLL
PLL
PLL
PLL
xtal
xtal
xtal
xtal
−
−
−
Preliminary specification
MASTER
OUTPUT
I
2
S-BUS
UDA1355H
PLL
PLL
PLL
PLL
xtal
xtal
xtal
xtal
xtal
xtal
−
SPDIF
I
SPDIF
−
−
−
I
SPDIF
I
SPDIF
SPDIF
2
2
2
LOCKS
INPUT
S-bus
S-bus
S-bus
PLL
ON