CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 54

• Manufacturer Part Number: CS4205-KQZ
• Description: IC CODEC AC97 I2S 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4205-KQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPs
• Interface Type: Serial (5-Wire)
• Resolution: 18 bit, 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1182

6. SERIAL DATA PORTS
6.1
The CS4205 implements two serial data output
ports and three serial data input ports that can be
used for digital docking or multi-channel expan-
sion. Each serial port consists of 4 signals: MCLK,
SCLK, LRCLK, and SDATA. The existing 256 Fs
BIT_CLK will be used as MCLK. The clock pins
are shared between all the serial ports with only the
SDATA pins being separate; SDOUT for the first
output port, SDO2 for the second output port, and
SDI[3:1] for the three input ports. Serial data is re-
ceived and transmitted on these ports every
AC-link frame.
The serial data port is controlled by the SDEN,
SDSC, SDI[3:1], and SDO2 bits in the Serial Port
Control Register (Index 6Ah). All the serial data
port pins are multiplexed with other functions and
cannot be used unless the other function is disabled
or powered down; see Section 9, Exclusive Func-
tions. Some audio DACs can run in an internal
SCLK mode where SCLK is internally derived
from MCLK and LRCLK. In this case, SCLK gen-
eration in the CS4205 is optional.
A feature has been designed into the CS4205 that
allows the phase of the internal DACs to be re-
54
Overview
GPIO1/SDOUT
GPIO0/LRCLK
LINE_OUT_R
LINE_OUT_L
SPDO/SDO2
EAPD/SCLK
BIT_CLK
35
36
44
47
43
6
48
Figure 15. Serial Data Port: Six Channel Circuit
1
2
3
4
1
2
3
4
SDATA
DEM#/SCLK
LRCK
MCLK
SDATA
LRCK
MCLK
DEM#/SCLK
CS4334
CS4334
AOUTR
AOUTR
AOUTL
AOUTL
8
5
8
5
1000pF
270K
270K
AGND
AGND
AGND
1000pF
270K
270K
versed. This DAC phase reversal is controlled by
the DPC bit in the Misc. Crystal Control Register
(Index 60h). This feature is necessary since the
phase response for external DACs is unknown and
the phase response of the internal DACs can vary
depending on the path determined by the DDM bit
in the AC Mode Control Register (Index 5Eh). This
feature guarantees that all DACs in a system have
the same phase response, maintaining the accuracy
of spatial cues.
In the CS4205, the volume of the serial port data is
controlled with the Serial Data Port Volume Con-
trol Registers (Index 6Eh, Address 06h - 07h).
However, there is no SRC available on this data, so
it is the responsibility of the controller or host soft-
ware to provide this functionality if desired.
6.2
For multi-channel expansion, the two serial data
output ports are used to send AC-link data to one or
two external stereo DACs to support up to a total of
six channels. The first serial port takes the digital
audio data from the SDOUT slots. The second seri-
al port takes the digital audio data from the SDO2
slots. See Table 14 on page 43 for the actual slots
used depending on configuration. Figure 15 shows
a six channel application using the CS4205.
+
+
+
+
ELEC
ELEC
ELEC
ELEC
10uF
10uF
10uF
10uF
+
+
ELEC
ELEC
10uF
10uF
Multi-Channel Expansion
47K
47K
AGND
AGND
47K
47K
560
560
560
560
220K
AGND
2700pF 2700pF
2700pF 2700pF
220K
AGND
AGND
Left Front
Right Front
Left Surround
Right Surround
Center
LFE
CS4205
DS489PP4