CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 35

• Manufacturer Part Number: CS4205-KQZ
• Description: IC CODEC AC97 I2S 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4205-KQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPs
• Interface Type: Serial (5-Wire)
• Resolution: 18 bit, 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1182

5.14
EAPD
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
Default
The PR[5:0] and the EAPD bits are powerdown control for different sections of the CS4205 as well as external am-
plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec-
tion of the CS4205 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must
be checked before writing to any mixer registers. See Section 10, Power Management, for more information on the
powerdown functions.
DS489PP4
EAPD
D15
Powerdown Control/Status Register (Index 26h)
D14
0
PR5
D13
External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power
down external amplifiers. The EAPD bit is mutually exclusive with the SDSC bit in the Serial
Port Control Register (Index 6Ah). The SDSC bit must be ‘clear’ before the EAPD bit may be
‘set’. If the SDSC bit is ‘set’, EAPD is a read-only bit and always returns ‘0’.
Internal Clock Disable. When ‘set’, the internal master clock is disabled (BIT_CLK running).
The only way to recover from setting this bit is through a Cold Reset (driving the RESET# sig-
nal active).
AC-link Powerdown. When ‘set’, the AC-link is powered down (BIT_CLK off). The AC-link can
be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RE-
SET# signal (primary audio codec only).
Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are
powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked be-
fore writing any mixer registers.
Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the volt-
age reference is still active). When clearing this bit, the ANL bit should be checked before writ-
ing any mixer registers.
Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the
DAC bit should be checked before sending any data to the DACs.
L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are
powered down. When clearing this bit, no valid data will be sent down the AC-link until the
ADC bit goes high.
Voltage Reference Ready Status. When ‘set’, the REF bit indicates the voltage reference is
at a nominal level.
Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-
trols are ready. When ‘clear’, no volume control registers should be written.
Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC-link.
When ‘clear’, the DACs will not accept any valid data.
L/R ADCs Ready Status. When ‘set’, the ADCs are ready to send data across the AC-link.
When ‘clear’, no data will be sent to the controller.
0000h. This value indicates all blocks are powered on. The lower four bits will change as the
CS4205 finishes an initialization and calibration sequence.
PR4
D12
PR3
D11
PR2
D10
PR1
D9
PR0
D8
D7
0
D6
0
D5
0
D4
0
REF
D3
ANL
D2
CS4205
DAC
D1
ADC
D0
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