CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 50

• Manufacturer Part Number: CS4205-KQZ
• Description: IC CODEC AC97 I2S 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4205-KQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPs
• Interface Type: Serial (5-Wire)
• Resolution: 18 bit, 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1182

5.34
EROF
ELOF
MROF
MLOF
AMOR
AROR
ALOR
Default
The IEC Config Register (Index 6Eh, Address 09h) enables error signaling for each potential error source. If a bit is
The IEC Wakeup Register (Index 6Eh, Address 0Ah) provides a mask for determining if an IEC will generate a wake-
The IEC Status Register (Index 6Eh, Address 0Bh) reflects the state of all internal error conditions. If a bit is ‘clear’,
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‘clear’, the corresponding source will not be monitored for errors. If a bit is ‘set’, the corresponding source will be
monitored and is able to signal an error condition. If an error occurs, the corresponding bit in the IEC Status Register
(Index 6Eh, Address 0Bh) will be ‘set’ and remains ‘set’ until the error is cleared, even if the error condition is no
longer present. This behavior is equivalent to “sticky” (edge sensitive) GPIO input pins.
up or GPIO_INT. If a bit is ‘0’, the corresponding error condition will not generate an interrupt. If a bit is ‘set’, the
corresponding error condition will generate an interrupt. For details about wakeup interrupts refer to the GPIO Pin
Wakeup Mask Register (Index 52h).
the corresponding source has not encountered an error condition or is not being monitored for errors. If a bit is ‘set’,
the corresponding source has encountered an error condition. The IEC bit in input slot 12 is a logic OR of all bits in
this register. An error condition is cleared by writing a ‘0’ to the corresponding bit of this register. Before clearing an
error condition, the controller should correct the error to prevent repeated error signaling. Table 20 lists all the inter-
nal error sources and corrective measures for each source.
EROF ELOF MROF MLOF
D15
Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh)
D14
IEC Bit
AMOR
AROR
MROF
MLOF
EROF
ALOR
ELOF
D13
Effects Engine Right Channel Overflow
Effects Engine Left Channel Overflow
Digital Mixer Right Channel Overflow
Digital Mixer Left Channel Overflow
Mic ADC Overrange
L/R ADC Right Channel Overrange
L/R ADC Left Channel Overrange
0000h
D12
Error Source
L/R ADC left channel overrange
L/R ADC right channel overrange
Mic ADC overrange
Digital mixer left channel overflow
Digital mixer right channel overflow
Effects engine left channel overflow
Effects engine right channel overflow GR[3:0] bits in reg 6Eh, addr 08h
Table 20. Internal Error Sources and Correction Methods
D11
0
AMOR AROR ALOR
D10
D9
D8
D7
0
Correction Method
GL[3:0] bits in reg 1Ch
GR[3:0] bits in reg 1Ch
GM[3:0] bits in reg 1Eh
GL[5:0] bits in reg 6Eh, addr 00h-05h
GR[5:0] bits in reg 6Eh, addr 00h-05h
GL[3:0] bits in reg 6Eh, addr 08h
D6
0
D5
0
D4
0
D3
0
D2
0
CS4205
D1
0
DS489PP4
D0
0