CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 30

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

30
4.2.1
4.2.2
Master Mode
As a clock master, the LRCKx and SCLKx of each serial port will operate as outputs. The two serial ports
may be independently placed into Master or Slave Mode. Each LRCKx and SCLKx are internally derived
from the MCLKx selected by the SP1_MCLK and SP2_MCLK signals as shown in
Slave Mode
In Slave Mode, SCLKx and LRCKx operate as inputs. Each serial port may be independently placed into
Slave Mode. The Left/Right clock signal, LRCKx, must be equal to the sample rate, Fs. The serial bit
clock, SCLKx, must be equal to 128x, 64x, 48x, or 32x Fs depending on the desired speed mode. Refer
to
If operating in Asynchronous Mode, LRCK1 and SCLK1 must be synchronously derived from the SP1’s
selected MCLK, and LRCK2 and SCLK2 must be synchronously derived from SP2’s selected MCLK. If
operating in Synchronous Mode, SCLK1, LRCK1, SCLK2 and LRCK2 must be synchronously derived
from the same MCLK. For more information on Synchronous and Asynchronous Modes, see
nous / Asynchronous Mode” on page
The speed of each serial port is automatically determined based on the input MCLKx to LRCKx ratio when
the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two
of MCLKx using either the MCLKx FREQ bits or the MDIV hardware control pin.
I²S, LJ or RJ Data Format
Table 6
SW Auto Mode Detect
HW Auto Mode Detect
Serial Data Format
for required serial bit clock to Left/Right clock ratios.
Mode
MCLK1
MCLK2
MCLK1 FREQ[1:0]
MCLK2 FREQ[1:0]
See
Figure 10. Master Mode Clock Generation
÷1.5
÷1.5
÷1
÷2
÷3
÷1
÷2
÷3
Table 3
Table 6. Slave Mode SCLK/LRCK Ratios
00
01
10
11
00
01
10
11
Table 7. MCLKx to LRCKx Ratios
an
29.
Table 4 on page 28
256, 384, 512, 768
Single Speed Mode
Single Speed Mode
Internal-MCLK1
Internal-MCLK2
32, 48, 64, 128
256, 512
SP1_MCLK
SP2_MCLK
MCLKx to LRCKx Ratio
SCLKx to LRCKx Ratio
for clock ratio configuration.
0
1
0
1
SP2_SPEED
SP1_SPEED
÷256
÷128
÷256
÷128
÷4
÷2
÷4
÷2
0
1
0
1
0
1
0
1
Double Speed Mode
Double Speed Mode
128, 192, 256, 384
Generated-LRCK1
Generated-SCLK1
Generated-LRCK2
Generated-SCLK2
32, 48, 64
128, 256
Figure
10.
CS42324
“Synchro-
DS721A6