CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 35

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686F1
8.5
8.5.1
8.5.2
8.5.3
DAC_SNGL_
VOL
7
Transition Control - Address 05h
DAC Single Volume (Bit 7)
Soft Ramp and Zero Cross Enable (Bits 6:5)
Invert Signal Polarity (Bits 4:1)
Function:
The AOUTA and AOUTB volume levels are independently controlled by the DAC Channel A & B Volume
Control Registers when this bit is cleared.
The volumes on AOUTA and AOUTB are locked together and determined by the DAC Channel A Volume
Control Register (07h) when this bit is set.
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1,024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1,024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
Function:
When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if
a board layout error has occurred or in other situations where a 180 phase shift is desirable.
Table 13 on page
DAC_SOFT
6
DAC_SOFT DAC_ZC
0
0
1
1
DAC_ZC
Table 13. Soft Cross or Zero Cross Mode Selection
35.
5
0
1
0
1
ADC_INV_
Changes take effect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
CHB
4
Table 10 on page
ADC_INV_
CHA
3
Mode
DAC_INV_
33.
CHB
2
DAC_INV_
CHA
1
DE_EMPH
CS4270
0
35