CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 23

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686F1
5.2.5
5.2.6
5.2.7
Internal Digital Loopback
Auto-Mute
DC Offset Calibration Using the High-Pass Filter
In Serial Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output
of the ADC is routed to the input of the DAC. This mode may be activated by setting the DIG_LOOPBK
bit in the ADC and DAC Control register (04h).
When this bit is set, the CS4270 ignores the status of the DAC_DIF(4:3) bits in register 04h. Any changes
made to the DAC_DIF(4:3) bits while the DIG_LOOPBK bit is set will have no impact on operation until
the DIG_LOOPBK bit is released, at which time the Digital Interface Format of the DAC will operate ac-
cording to the format selected in the DAC_DIF(4:3) bits. While the DIG_LOOPBK bit is set, data will be
present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.
The Auto-Mute function is controlled by the status of the Auto Mute bit in the Mute register. When set, the
DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single
sample of non-static data will release the mute. Detection and muting are done independently for each
channel. The common mode on the output will be retained and the Mute Control pin for that channel will
become active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and Zero Cross bits in the Transition and Control register. The Auto Mute bit is set by default.
At the system level, the input circuitry driving the CS4270 may generate a small DC offset level into the
A/D converter which could result in possibly yielding "clicks" when switching between devices in a multi-
channel system. The CS4270 includes one high-pass filter per channel (see
for CH A (Bit 7)” on page 34
this system problem.
Running the CS4270 with the high-pass filter enabled, then freezing the stored DC offset value eliminates
offsets anywhere in the signal path between the calibration point and the CS4270.
Single-Speed
Double-Speed
Quad-Speed
Speed Mode
MCLK/LRCK
1,024
Table 7. Clock Ratios - Serial Control Port Mode (Continued)
256
384
512
768
128
192
256
384
512
128
192
256
64
96
and
32, 48, 64, 96, 128
32, 48, 64, 96, 128
32, 48, 64, 96, 128
32, 48, 64, 128
32, 48, 64, 128
SCLK/LRCK
“ADC High Pass Filter Freeze for CH A (Bit 7)” on page
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
Slave Mode
LRCK MCLK_FREQ2 MCLK_FREQ1 MCLK_FREQ0
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
“ADC High Pass Filter Freeze
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
34) to alleviate
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
CS4270
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