CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 32

IC CODEC 24BIT 105DB 24TSSOP

CS4270-DZZ

Manufacturer Part Number
CS4270-DZZ
Description
IC CODEC 24BIT 105DB 24TSSOP
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheets

Specifications of CS4270-DZZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 105
Voltage - Supply, Analog
3.1 V ~ 5.25 V
Voltage - Supply, Digital
3.1 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Audio Codec Type
Stereo
No. Of Adcs
1
No. Of Dacs
1
No. Of Input Channels
3
No. Of Output Channels
3
Adc / Dac Resolution
24bit
Sampling Rate
216kSPS
Ic Interface Type
I2C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1002 - BOARD EVAL FOR CS4270 CODEC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1622

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4270-DZZ
Manufacturer:
CIRRUS
Quantity:
9
Part Number:
CS4270-DZZ
Manufacturer:
CIRRUS
Quantity:
62
32
8. REGISTER DESCRIPTION
** All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted**
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
Freeze
ID3
7
7
Device ID - Address 01h
Function:
This register is read only. Bits 7 through 4 are the device ID, which is 1100b (0Ch) and the remaining bits
REV[3:0] are for the device revision.
Power Control - Address 02h
Freeze (Bit 7)
PDN_ADC (Bit 5)
PDN_DAC (Bit 1)
Power Down (Bit 0)
Function:
This function allows changes to registers 05h–08h without the changes taking effect until the Freeze bit
is cleared. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all
changes, then clear the Freeze bit.
Function:
The ADC portion of the device will enter a low-power state whenever this bit is set.
Function:
The DAC portion of the device enters a low-power state when this bit is set.
Function:
The device enters a low-power state when this bit is set. The contents of all registers are retained when
the device is in power-down.
Reserved
ID2
6
6
PDN_ADC
ID1
5
5
Reserved
ID0
4
4
Reserved
REV3
3
3
Reserved
REV2
2
2
PDN_DAC
REV1
1
1
CS4270
REV0
DS686F1
PDN
0
0

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