MPC8560PX833LC Freescale Semiconductor, MPC8560PX833LC Datasheet - Page 49

• Manufacturer Part Number: MPC8560PX833LC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

10 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
Table 39
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see
(reference)(state)
t
(V) relative to the t
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
JTDVKH
provides the JTAG AC timing specifications as defined in
Figure
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
Table 39. JTAG AC Timing Specifications (Independent of SYSCLK)
for inputs and t
Parameter
JTG
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
clock reference (K) going to the high (H) state or setup time. Also, t
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
(first two letters of functional block)(reference)(state)(signal)(state)
Table
2).
TMS, TDI
TMS, TDI
TDO
TDO
TDO
TCLK
TCLK
.
.
t
JTGR
Symbol
t
t
t
t
t
t
t
t
t
t
t
JTKHKL
JTDVKH
JTDXKH
JTKLOV
JTKLDX
JTKLOZ
JTKLDV
JTKLOX
JTKLDZ
JTIVKH
JTIXKH
t
t
TRST
f
JTG
JTG
& t
JTGF
2
(first two letters of functional block)(signal)(state)
Min
30
15
25
20
25
0
0
4
0
4
4
3
3
Figure 32
TCLK
for outputs. For example,
Max
33.3
to the midpoint of the signal
20
25
19
—
—
—
—
—
—
—
—
2
9
through
JTDXKH
JTG
clock reference (K)
1
symbolizes JTAG
MHz
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
35.
Notes
5, 6
—
—
—
6
3
4
4
5
5
JTAG
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