MPC8560PX833LC Freescale Semiconductor, MPC8560PX833LC Datasheet - Page 36

• Manufacturer Part Number: MPC8560PX833LC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Local Bus
36
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance
for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to local bus clock for DLL bypass mode. Timings may be negative with respect to the local bus
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from OV
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
8. Guaranteed by characterization.
9. Guaranteed by design.
(reference)(state)
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
high (H), in this case for clock one(1). Also, t
high (H), with respect to the output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
complementary signals at OV
in question for 3.3-V signaling levels.
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
through the component pin is less than or equal to the leakage current specification.
LBKHKT
.
LBOTOT
Parameter
Table 32. Local Bus General Timing Parameters—DLL Bypassed (continued)
for inputs and t
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
(First two letters of functional block)(reference)(state)(signal)(state)
DD
/2.
DD
/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
POR Configuration
LBKHOX
(default)
(default)
(default)
(default)
(default)
(default)
symbolizes local bus timing (LB) for the t
Symbol
t
t
t
t
t
t
t
LBKHOV4
LBKLOV2
LBKLOV3
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
(First two letters of functional block)(signal)(state)
1
Min
-3.2
-2.3
-3.2
-2.3
for outputs. For example, t
—
—
—
—
—
LBK
LBK
Max
-0.1
1.4
1.5
0.2
1.5
0.2
1.5
—
—
0
0
clock reference (K) to go
clock reference (K) goes
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
DD
LBIXKH1
of the signal
Notes
4
4
4
4
4
7
7