MC7457RX867NC Freescale Semiconductor, MC7457RX867NC Datasheet - Page 55

• Manufacturer Part Number: MC7457RX867NC
• Description: IC MPU RISC 32BIT 483FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7457RX867NC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 867MHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Family Name: MPC74xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 867MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3/1.5/1.8/2.5V
• Operating Supply Voltage (max): 1.35/1.575/2.625V
• Operating Supply Voltage (min): 1.25/1.425/1.71V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 483
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

9.6
The MPC7457 requires high-resistive (weak: 4.7-k
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7457 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OV
proper device operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OV
LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4].
For the MPC7457, 483 BGA, the pins that must be pulled up to OV
the pins that must be pulled down are: L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise
be pulled up through a pull-up resistor (weak or stronger: 4.7–1 k
signal.
In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or
stronger: 4.7–1 k
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250
(see
pull-down resistors (1 k
erroneous switching due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7457
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up
through weak (10-k
RISC Microprocessor Family Users’ Manual for more information about this mode), or they may be
otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.
Preliminary studies have shown the additional power draw by the MPC7457 input receivers to be
negligible and, in any event, none of these measures are necessary for proper device operation. The
snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak
pull-down resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through
weak pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: D[0:63] and DP[0:7].
Freescale Semiconductor
Table
Pull-Up/Pull-Down Resistor Requirements
Z
16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
0
Typical
Maximum
Ω
) if it is used by the system. This pin is CKSTP_OUT.
Ω
) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450
Ω
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Impedance
or less) are recommended to configure these signals in order to protect against
Table 21. Impedance Characteristics
V
DD
= 1.5 V, OV
DD
= 1.8 V ± 5%, T
Ω
) pull-up resistors on several control pins of the bus
Processor Bus
33–42
31–51
j
= 5°–85°C
Ω
) to prevent erroneous assertions of this
DD
are: LSSD_MODE and TEST[0:5];
DD
or down to GND to ensure
L3 Bus
34–42
32–44
System Design Information
Unit
Ω
Ω
DD
are:
Ω
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