MC68040FE25A Freescale Semiconductor, MC68040FE25A Datasheet - Page 264

• Manufacturer Part Number: MC68040FE25A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.6 FLOATING-POINT EXCEPTIONS
There are two classes of floating-point-related exceptions: nonarithmetic floating-point
exceptions and arithmetic floating-point exceptions. The latter relates to the handling of
arithmetic exceptions caused by floating-point activity, and the former includes
unimplemented floating-point instructions and unsupported data types not related to the
handling of arithmetic exceptions. Format error and FTRAPcc exceptions may seem to be
floating-point related, but are considered IU exceptions (see Section 8 Exception
Processing). The following sections detail floating-point exceptions and how the
MC68040 and M68040FPSP handle them. Table 9-9 lists the vector numbers related to
floating-point exceptions.
The following paragraphs detail nonarithmetic floating-point exceptions.
9.6.1 Unimplemented Floating-Point Instructions
F-line instructions are instruction word patterns with bits 15–12 that have an $F encoding,
causing F-line exceptions. These instructions are termed unimplemented floating-point
instructions and cause an unimplemented floating-point exception. The MC68040
recognizes some F-line instructions, such as the FMUL and CPUSH, which do not cause
F-line exceptions. There are some F-line instructions that the MC68040 recognizes as
valid MC68881/MC68882 floating-point instruction patterns, but as floating-point
instructions that the processor cannot complete in hardware. Table 9-10 lists the floating-
point instructions that are unimplemented and therefore cause an unimplemented
instruction exception.
If the processor encounters an F-line instruction and the instruction patterns do not match
either of the above two cases, the processor takes an F-line illegal exception. F-line illegal
exceptions are discussed further in Section 8 Exception Processing. The processor
generates an exception with vector number 11 and pushes a four-word stack frame format
$0 on the system stack. An illegal instruction exception is also reported when a breakpoint
acknowledge bus cycle is run and terminated with either a transfer acknowledge (TA) or
transfer error acknowledge (TEA) signal. Since the unimplemented floating-point
9-20
Number
Vector
11
48
49
50
51
52
53
54
55
Vector Offset
Table 9-9. Floating-Point Exception Vectors
(Hex)
02C
0C0
0C4
0C8
0CC
0D0
0D4
0D8
0DC
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Floating-Point Unimplemented Instruction
Floating-Point Branch or Set on Unordered Condition
Floating-Point Inexact Result
Floating-Point Divide by Zero
Floating-Point Underflow
Floating-Point Operand Error
Floating-Point Overflow
Floating-Point SNAN
Floating-Point Unimplemented Data Type
(also used for F-line instruction)
Assignment
MOTOROLA