MC68EC040RC40A Freescale Semiconductor, MC68EC040RC40A Datasheet - Page 274

• Manufacturer Part Number: MC68EC040RC40A
• Description: IC MPU 32BIT 40MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC40A

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -

9.7.3.2 NONMASKABLE EXCEPTION CONDITIONS. If an FMOVE to byte, word, or long
word has a source operand that is too large to be represented in the specified destination
integer format (integer overflow, NAN, infinity) or if the source operand is equal to the
largest negative integer representable in the specified destination integer format
(erroneous MC68040 condition), the processor immediately takes a post-instruction
exception. Instruction execution continues at the M68040FPSP OPERR exception
handler.
If the M68040FPSP determines a nonmaskable erroneous MC68040 condition caused the
exception, it stores the largest negative integer representable in the given destination
integer format (–2
OPERR exception handler then returns the processor to normal processing. If an integer
overflow or an FMOVE to byte, word, or long word with a source of infinity causes the
exception, then the destination is written with the largest positive or negative integer that
can be represented in the given format. If an FMOVE to byte of word or long word with a
source of NAN causes the exception, then the most significant 8, 16, or 32 bits,
respectively, are written to the destination. Next, the M68040FPSP OPERR exception
handler checks to see if the user OPERR exception handler is enabled.
The user OPERR exception handler must execute an FSAVE as its first floating-point
instruction. Table 9-16 lists the floating-point state frame fields for OPERR exceptions
resulting from the execution of opclass 010 or 000 (register-to-register or memory-to-
register) instructions and opclass 011 (register-to-memory) instructions defined for the use
by the supervisor exception handler.
9-30
b. If the user OPERR exception handler is enabled and the destination floating-point
a. If the user OPERR exception handler is disabled, an exception-causing INEX1 or
b. If the user OPERR exception handler is enabled and the destination is a floating-
data register is not modified, an OPERR exception is posted. The next floating-point
instruction that is encountered takes a pre-instruction exception. The OPERR entry
in the processor’s vector table points to the M68040FPSP OPERR exception
handler. Once the M68040FPSP OPERR exception handler recognizes the operand
error as a maskable condition, it does not modify the destination or pass control to
the user OPERR exception handler.
INEX2 condition exists, and the user INEX exception handler is enabled. The
M68040FPSP OPERR exception handler restores the FPU to its exceptional state,
cleans up the stack to the conditions prior to execution, and continues instruction
execution at the user INEX exception handler. No parameters are passed to the user
INEX exception handler since the M68040FPSP OPERR exception handler provides
the illusion that it never existed. Otherwise, the M68040FPSP OPERR exception
handler returns the processor to normal processing.
point data register, then the M68040FPSP exception handler does not modify the
register. The M68040FPSP OPERR exception handler restores the FPU to its
exceptional state, cleans up the stack to the conditions prior to execution, and
continues instruction execution at the user OPERR exception handler. No
parameters are passed to the user OPERR exception handler since the
M68040FPSP OPERR exception handler provides the illusion that it never existed.
7
for byte, –2
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for word, and –2
31
for long word). The M68040FPSP
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