MC68EC040RC40A Freescale Semiconductor, MC68EC040RC40A Datasheet - Page 154

• Manufacturer Part Number: MC68EC040RC40A
• Description: IC MPU 32BIT 40MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC40A

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -

Clock 1 (C1)
Clock 2 (C2)
7.4.2 Line Read Transfer
The processor uses line read transfers to access a 16-byte operand for a MOVE16
instruction and to support cache line filling. A line read accesses a block of four long
words, aligned to a 16-byte memory boundary, by supplying a starting address that points
to one of the long words and requiring the memory device to sequentially drive each long
word on the data bus. The selected device must internally increment A3 and A2 of the
supplied address for each transfer, causing the address to wrap around at the end of the
block. The address and transfer attributes supplied by the processor remain stable during
the transfers, and the selected device terminates each transfer by driving the long word on
7-12
The read cycle starts in C1. During the first half of C1, the processor places valid values
on the address bus and transfer attributes. For user and supervisor mode accesses,
which the corresponding memory unit translates, the user-programmable attribute
signals (UPAx) are driven with the values from the matching user bits (U1 and U0). The
transfer type (TTx) and transfer modifier (TMx) signals identify the specific access type.
The read/write (R/W) signal is driven high for a read cycle. Cache inhibit out (CIOUT) is
asserted since the access is identified as noncachable. Refer to Section 3 Memory
Management Unit (Except MC68EC040 and MC68EC040V) for information on the
M68040 and MC68LC040 memory units and Appendix B MC68EC040 for information
on the MC68EC040 memory unit.
The processor asserts transfer start (TS) during C1 to indicate the beginning of a bus
cycle. If not already asserted from a previous bus cycle, the transfer in progress ( TIP)
signal is also asserted at this time to indicate that a bus cycle is active.
During the first half of the clock after C1, the processor negates T S. The selected
peripheral device uses R/W, SIZ1, SIZ0, A1, and A0 to place its information on the data
bus. With the exception of the R/W signal, these signals also select any or all of the
operand bytes (D31–D24, D23–D16, D15–D8, and D7–D0). If the first clock after C1 is
not a wait state (CW), then the selected peripheral device asserts the transfer
acknowledge (TA) signal.
At the end of the first clock cycle after C1, the processor samples the level of TA and
latches the current value on the data bus; the bus cycle terminates, and the data is
passed to the processor’s appropriate memory unit if TA is asserted. If T A is not
recognized asserted at the end of the clock cycle, the processor ignores the data and
inserts a wait state instead of terminating the transfer. The processor continues to
sample TA on successive rising edges of BCLK until TA is recognized asserted. The
data is then passed to the processor’s appropriate memory unit.
When the processor recognizes TA at the end of a clock and terminates the bus cycle,
TIP remains asserted if the processor is ready to begin another bus cycle. Otherwise,
the processor negates TIP during the first half of the next clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
MOTOROLA