CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 52

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Real Address Mode Only
Either Mode
Protected Virtual Address Mode Only
10. For segment load operations, the CPL, RPL and DPL
80C286 Instruction Set Summary
FUNCTION
DATA TRANSFER
MOV = Move
Register to Register/Mem-
ory
Register/Memory to Regis-
ter
Immediate to Register/Mem-
ory
Immediate to Register
Memory to Accumulator
8. LOCK does not remain active between all operand
1. This is a protected mode instruction. Attempted execu-
2. A segment overrun exception (13) will occur if a word
3. This instruction may be executed in real address mode to
4. The IOPL and NT fields will remain 0.
5. Processor extension segment overrun interrupt (9) will
6. An exception may occur, depending on the value of the
7. LOCK is automatically asserted regardless of the pres-
9. A general protection exception (13) will occur if the mem-
tion in real address mode will result in an undefined
opcode exception (6).
operand references at offset FFFF(H) is attempted.
initialize the CPU for protected mode.
occur if the operand exceeds the segment limit.
operand.
transfers.
ory operand cannot be used due to either a segment limit
or access rights violation. If a stack segment limit is vio-
lated, a stack segment overrun exception (12) occurs.
must agree with privilege rules to avoid an exception.
The segment must be present to avoid a not-present
exception (11). If the SS register is the destination and a
ence or absence of the LOCK instruction prefix.
1010000w addr-low
FORMAT
1000100w mod
1000101w mod
1100011w
1011w reg data
r/m
r/m
r/m
mod 000
reg
reg
data if w =
addr-high
data
1
80C286
52
11. All segment descriptor accesses in the GDT or LDT made
12. JMP, CALL, INT, RET, IRET instructions referring to
13. A general protection exception (13) occurs if CPL ≠ 0.
14. A general protection exception (13) occurs if CPL > IOPL.
15. The IF field of the flag word is not updated if CPL > IOPL.
16. Any violation of privilege rules as applied to the selector
17. If the starting address of the memory operand violates a
18. The destination of an INT, JMP, CALL, RET or IRET
data if
w = 1
segment not-present violation occurs, a stack exception
(12) occurs.
by this instruction will automatically assert LOCK to main-
tain descriptor integrity in multiprocessor systems.
another code segment will cause a general protection
exception (13) if any privilege rule is violated.
The IOPL field is updated only if CPL = 0.
operand does not cause a protection exception; rather,
the instruction does not return a result and the zero flag
is cleared.
segment limit, or an invalid access is attempted, a gen-
eral protection exception (13) will occur before the ESC
instruction is executed. A stack segment overrun excep-
tion (12) will occur if the stack limit is violated by the
operand’s starting address. If a segment limit is violated
during an attempted data transfer then a processor
extension segment overrun exception (9) occurs.
instruction must be in the defined limit of a code segment
or a general protection exception (13) will occur.
CLOCK COUNT
REAL
ADDRES
S
MODE
2, 3
(Note 59)
2, 5
(Note 59)
2, 3
(Note 59)
5
2
PRO-
TECTED
VIRTUAL
ADDRESS
MODE
2, 3
(Note 59)
2, 5
(Note 59)
2, 3
(Note 59)
2
5
COMMENTS
REAL
ADDRES
S
MODE
2
2
2
2
PRO-
TECTED
VIRTUAL
ADDRESS
MODE
9
9
9
9