CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 16

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Reserved Memory Locations
The 80C286 reserves two fixed areas of memory in real
address mode (see Figure 7); system initialization area and
interrupt table area. Locations from addresses FFFF0(H)
through FFFFF(H) are reserved for system initialization. Initial
execution begins at location FFFF0(H). Locations 00000(H)
through 003FF(H) are reserved for interrupt vectors.
Interrupts
Table 9 shows the interrupt vectors reserved for exceptions
and interrupts which indicate an addressing error. The
exceptions leave the CPU in the state existing before
attempting to execute the failing instruction (except for
PUSH, POP, PUSHA, or POPA). Refer to the next section
on protected mode initialization for a discussion on excep-
tion 8.
FIGURE 7. 80C286 REAL ADDRESS MODE INITIALLY
RESERVED MEMORY LOCATIONS
INITIAL CS:IP VALUE IS F000:FFF0
INTERRUPT POINTER
INTERRUPT POINTER
INTERRUPT POINTER
RESET BOOTSTRAP
FOR VECTOR 255
PROGRAM JUMP
FOR VECTOR 1
FOR VECTOR 0
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•
•
•
•
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FFFFFH
FFFF0H
3FFH
3FCH
7H
4H
3H
0H
80C286
16
Protected Mode Initialization
To prepare the 80C286 for protected mode, the LIDT
instruction is used to load the 24-bit interrupt table base and
16-bit limit for the protected mode interrupt table. This
instruction can also set a base and limit for the interrupt vec-
tor table in real address mode. After reset, the interrupt table
base is initialized to 000000(H) and its size set to 03FF(H).
These values are compatible with 80C86 and 80C88 soft-
ware. LIDT should only be executed in preparation for pro-
tected mode.
Shutdown
Shutdown occurs when a severe error is detected that prevents
further instruction processing by the CPU. Shutdown and halt
are externally signalled via a halt bus operation. They can be
distinguished by A
real address mode, shutdown can occur under two conditions:
• Exceptions 8 or 13 happen and the IDT limit does not
• A CALL INT or PUSH instruction attempts to wrap around
An NMI input can bring the CPU out of shutdown if the IDT
limit is at least 000F(H) and SP is greater than 0005(H), oth-
erwise shutdown can only be exited via the RESET input.
include the interrupt vector.
the stack segment when SP is not even.
1
HIGH for halt and A
1
LOW for shutdown. In