CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 50

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Waveforms
ASSUMING WORD-ALIGNED MEMORY OPERAND. IF ODD ALIGNED, 80C286 TRANSFERS TO/FROM MEMORY BYTE-AT-A-TIME WITH TWO MEMORY
CYCLES.
NOTES:
54. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus opera-
55. To prevent a second processor extension data operand transfer, the worst case maximum time (Shown above) is
NOTES:
56. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
57. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
58. The data bus is only guaranteed to be in a high impedance state at the time shown.
CYCLE TYPE
COD INTA
A23 - A0
S1 • S0
PEACK
PEREQ
tion will be either a memory read at operand address or I/O read at port address 00FA(H).
3 x
number of extra T
M/IO,
CLK
V
V
CYCLE TYPE
BUS
1
CH
CL
- 12A
COD/INTA
A
RESET
T
PEACK
S1 • S0
23
I
LOCK
HLDA
DATA
BUS
CLK
MAX
- A
BHE
M/IO
12A
φ2
(Continued)
V
V
0
CH
CL
C
-
states added to either the first or second bus operation of the processor extension data operand transfer sequence.
4
MIN
FIGURE 38. 80C286 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
φ1
. The actual configuration dependent, maximum time is: 3 x
(SEE NOTE 54)
I/O READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT.
(SEE NOTE 55)
T
S
19
φ2
FIGURE 39. INITIAL 80C286 PIN STATE DURING RESET
12B
UNKNOWN
UNKNOWN
UNKNOWN
φ2
UNKNOWN
UNKNOWN
(SEE NOTE 56)
φ1
4
1
T
X
16
T
φ2
C
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
80C286
φ2
16 CLK PERIODS
φ1
50
5
AT LEAST
T
X
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O PORT
ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
φ1
φ2
T
S
13
12B
φ2
φ1
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
T
X
1
(SEE NOTE 57)
15
13
13
- 12A
φ1
φ2
MAX
T
(SEE NOTE 58)
C
7
φ1
-
φ2
4
MIN
T
I
+ N x 2 x
φ2
φ1
T
1
6
I
. N is the