CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 20

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Segment Descriptor Cache Registers
A segment descriptor cache register is assigned to each of
the four segment registers (CS, SS, DS, ES). Segment
descriptors are automatically loaded (cached) into a seg-
ment descriptor cache register (Figure 12) whenever the
associated segment register is loaded with a selector.
Only segment descriptors may be loaded into segment
descriptor cache registers. Once loaded, all references to
that segment of memory use the cached descriptor informa-
tion instead of reaccessing the descriptor. The descriptor
cache registers are not visible to programs. No instructions
exist to store their contents. They only change when a seg-
ment register is loaded.
Selector Fields
A protected mode selector has three fields: descriptor entry
index, local or global descriptor table indicator (T
tor privilege (RPL) as shown in Figure 13. These fields select
one of two memory based tables of descriptors, select the
appropriate table entry and allow high-speed testing of the
selector's privilege attribute (refer to privilege discussion
below).
† MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES
DESTINATION
DESTINATION
SELECTOR
OFFSET
COUNT
WORD
NAME
TYPE
DPL
TABLE 12. GATE DESCRIPTOR FORMAT FIELD
P
+7
+5
+3
+1
7
15
P DPL 0
FIGURE 11. GATE DESCRIPTOR
Selector
VALUE
Offset
0 - 31
16-Bit
DESTINATION SELECTOR
16-Bit
0 - 3
DESTINATION OFFSET
4
5
6
7
0
1
TYPE
RESERVED †
Call Gate
Task Gate
Interrupt Gate
Trap Gate
Descriptor Contents are not valid
Descriptor Contents are valid
Descriptor Privilege Level
Number of words to copy from callers
stack to called procedures stack. Only
used with call gate.
Selector to the target code segment
(call, interrupt or selector Trap Gate).
Selector to the target task state seg-
ment (Task Gate).
Entry point within the target code seg-
ment
8
0 7
X X X
7
DESCRIPTION
WORD COUNT
15 - 0
15 - 0
4 - 0
X X
I
), and selec-
0
0
+6
+4
+2
0
80C286
20
Local and Global Descriptor Tables
Two tables of descriptors, called descriptor tables, contain all
descriptors accessible by a task at any given time. A descriptor
table is a linear array of up to 8192 descriptors. The upper 13
bits of the selector value are an index into a descriptor table.
Each table has a 24-bit base register to locate the descriptor
table in physical memory and a 16-bit limit register that confine
descriptor access to the defined limits of the table as shown in
Figure 14. A restartable exception (13) will occur if an attempt is
made to reference a descriptor outside the table limits.
One table, called the Global Descriptor table (GDT), con-
tains descriptors available to all tasks. The other table,
called the Local Descriptor Table (LDT), contains descriptors
that can be private to a task. Each task may have its own pri-
vate LDT. The GDT may contain all descriptor types except
interrupt and trap descriptors. The LDT may contain only
segment, task gate, and call gate descriptors. A segment
cannot be accessed by a task if its segment descriptor does
not exist in either descriptor table at the time of access.
15 - 3 Index
BITS
1 - 0
47
2
ACCESS
RIGHTS
FIGURE 12. DESCRIPTOR CACHE REGISTERS
Requested Privilege Level
(RPL)
Table Indicator (TI)
40 39
SEGMENT DESCRIPTOR CACHE REGISTERS
FIGURE 13. SELECTOR FIELDS
(AUTOMATICALLY LOADED BY CPU)
SEGMENT PHYSICAL
NAME
BASE ADDRESS
15
CS
DS
SS
ES
(LOADED BY PROGRAM)
SEGMENT SELECTORS
SEGMENT REGISTERS
PROGRAM VISIBLE
PROGRAM INVISIBLE
15
SELECTOR
Indicates Selector Privilege
Level Desired
TI = 0 Use Global Descrip-
tor Table (GDT)
TI = 1 Use Local Descriptor
Table (LDT)
Select Descriptor Entry In
Table
16 15
INDEX
8
0
SEGMENT SIZE
7
FUNCTION
TI
2 1 0
0
RPL