MPC850DSLZQ50BU Freescale Semiconductor, MPC850DSLZQ50BU Datasheet - Page 17

• Manufacturer Part Number: MPC850DSLZQ50BU
• Description: IC MPU PWRQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC850DSLZQ50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Num
B33a
B34a
B34b
B35a
B35b
B34
B35
B36
B37
B38
B39
B40
B41
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST4 in the corresponding
word in the UPM
A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST1 in the corresponding
word in the UPM
A[6–31] and D[0–31] to CS valid
- as requested by CST2 in the
corresponding word in UPM
A[6–31] to CS valid - as
requested by control bit BST4 in
the corresponding word in UPM
A[6–31] and D[0–31] to BS valid
- as requested by BST1 in the
corresponding word in the UPM
A[6–31] and D[0–31] to BS valid
- as requested by control bit
BST2 in the corresponding
word in the UPM
A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
UPWAIT valid to CLKOUT
falling edge
CLKOUT falling edge to
UPWAIT valid
AS valid to CLKOUT rising edge
A[6–31], TSIZ[0–1], RD/WR,
BURST, valid to CLKOUT rising
edge.
TS valid to CLKOUT rising edge
(setup time)
11
Characteristic
10
10
Table 6. Bus Operation Timing
13.00
13.00
5.00
3.00
8.00
3.00
8.00
3.00
6.00
1.00
7.00
7.00
7.00
Min
50 MHz
12.00
Max
—
—
—
—
—
—
—
—
—
—
—
—
13.00
21.00
13.00
21.00
8.00
6.00
6.00
6.00
6.00
1.00
7.00
7.00
7.00
Min
66 MHz
14.00
Max
—
—
—
—
—
—
—
—
—
—
—
—
1
(continued)
17.00
17.00
11.00
11.00
6.00
4.00
4.00
4.00
6.00
1.00
7.00
7.00
7.00
Min
80 MHz
13.00
Max
—
—
—
—
—
—
—
—
—
—
—
—
FFACT
0.250
0.250
0.500
0.750
0.250
0.500
0.750
0.250
—
—
—
—
—
Cap Load
(default
50 pF)
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
Bus Signal Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17