IDT79RC32H434-266BC IDT, Integrated Device Technology Inc, IDT79RC32H434-266BC Datasheet - Page 34

• Manufacturer Part Number: IDT79RC32H434-266BC
• Description: IC MPU 32BIT CORE 266MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-266BC

• Processor Type: MIPS32 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32H434-266BC

Using the EJTAG Probe
Using the EJTAG Probe
Using the EJTAG Probe
Using the EJTAG Probe
be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k because a low value reduces crosstalk on the cable to
the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33 . Recommended resistor values have ± 5% toler-
ance.
JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The
pull-up resistor value of around 47 k should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the
signals of the chip with EJTAG.
actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system
reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a
voltage reference that drops rapidly to below 0.5V when the target system loses power, even with a capacitive load of 25pF. The probe can thus detect
the lost power condition.
P P P P hase-Locked Loop (PLL)
to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limited range.
PLL Filters
circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 21. Because the
optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as
starting points for further experimentation within your specific application.
IDT RC32434
hase-Locked Loop (PLL)
hase-Locked Loop (PLL)
hase-Locked Loop (PLL)
In Figure 20, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must
If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the
If a probe is used, the RST* signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is
For additional information on EJTAG, refer to Chapter 17 of the RC32434 User Reference Manual.
The phase-locked loop (PLL) multiplies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector
It is recommended that the system designer provide a filter network of passive components for the PLL analog and digital power supplies.
V
V
cc
ss
10 ohm
Figure 21 PLL Filter Circuit for Noisy Environments
10
1
µ
F
0.1
34 of 53
µ
F
100 pF
V
V
V
V
RC32434
cc
ss
cc
ss
PLL
PLL
PLL
PLL
January 19, 2006
The
PLL