IDT79RC32H434-266BC IDT, Integrated Device Technology Inc, IDT79RC32H434-266BC Datasheet - Page 12

• Manufacturer Part Number: IDT79RC32H434-266BC
• Description: IC MPU 32BIT CORE 266MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-266BC

• Processor Type: MIPS32 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32H434-266BC

Boot Configuration Vector
Boot Configuration Vector
Boot Configuration Vector
Boot Configuration Vector
tion vector read in by the RC32434 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register.
IDT RC32434
The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configura-
MADDR[3:0]
MADDR[5:4]
MADDR[6]
MADDR[7]
MADDR[10:8]
Signal
CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multi-
plies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For
master clock input frequency constraints, refer to Table 3.2 in the RC32434 User Man-
ual.
0x0 - PLL Bypass
0x1 - Multiply by 3
0x2 - Multiply by 4
0x3 - Multiply by 5 - Reserved
0x4 - Multiply by 5
0x5 - Multiply by 6 - Reserved
0x6 - Multiply by 6
0x7 - Multiply by 8
0x8 - Multiply by 10
0x9 through 0xF - Reserved
External Clock Divider. This field specifies the value by which the IPBus clock
(ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock
output on the EXTCLK pin.
0x0 - Divide by 1
0x1 - Divide by 2
0x2 - Divide by 4
0x3 - reserved
Endian. This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
Reset Mode. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for minimum of 4000 clock cycles. If the internal boot
configuration vector is selected, the expiration of an 18-bit counter operating at the
master clock input (CLK) frequency is used as the PLL stabilization delay.
0x1 - Reserved
PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial
value of the EN bit in the PCIC register is determined by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
0x6 - reserved
0x7 - reserved
Table 3 Boot Configuration Encoding (Part 1 of 2)
(EN initial value is zero)
(EN initial value is zero)
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Name/Description
January 19, 2006