EZ80L92AZ020EC00TR Zilog, EZ80L92AZ020EC00TR Datasheet - Page 53
EZ80L92AZ020EC00TR
Manufacturer Part Number
EZ80L92AZ020EC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ020EC00T
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Table 12. Vectored Interrupt Operation (Continued)
PS013014-0107
Memory
Mode
ADL Mode
Non-maskable Interrupts
ADL
Bit
An active Low input on the NMI pin generates an interrupt request to the eZ80 CPU. This
non-maskable interrupt is always serviced by the eZ80 CPU, regardless of the state of the
Interrupt Enable flags (IEF1 and IEF2). The non-maskable interrupt is prioritized higher
than all maskable interrupts. The response of the eZ80 CPU to a non-maskable interrupt is
described in detail in eZ80
1
MADL
Bit
1
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
The ADL mode bit remains set to 1.
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}.
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
The ending Program Counter is { 00h, PC[15:0] }.
The interrupt service routine must end with RETI.L
←
←
0
0
®
CPU User Manual (UM0077).
Product Specification
Interrupt Controller
eZ80L92 MCU
47
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