EZ80L92AZ020EC00TR Zilog, EZ80L92AZ020EC00TR Datasheet - Page 186
EZ80L92AZ020EC00TR
Manufacturer Part Number
EZ80L92AZ020EC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ020EC00T
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PS013014-0107
ZDI Read Registers—Low, High, and Upper
The ZDI register Read-Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See
Table 104. ZDI Read Registers—Low, High and Upper (ZDI_RD_L = 10h,
ZDI_RD_H = 11h, and ZDI_RD_U = 12h in the ZDI Register Read-Only
Address Space)
Bit
Position
7
zdi_active
6
5
halt_SLP
4
ADL
3
MADL
2
IEF1
[1:0]
Reserved
Bit
Reset
CPU Access
Note: R = Read-only.
Value Description
00
0
1
0
0
1
0
1
0
1
0
1
R
7
0
The CPU is not functioning in ZDI mode.
The CPU is currently functioning in ZDI mode.
Reserved.
eZ80L92 is not currently in HALT or SLEEP mode.
eZ80L92 is currently in HALT or SLEEP mode.
The CPU is operating in Z80 MEMORY mode.
(ADL bit = 0).
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1).
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved.
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R
2
0
ZiLOG Debug Interface
eZ80L92 MCU
R
1
0
Table
104.
R
0
0
180
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