EZ80L92AZ020EC00TR Zilog, EZ80L92AZ020EC00TR Datasheet - Page 132

• Manufacturer Part Number: EZ80L92AZ020EC00TR
• Description: IC EZ80 MPU 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020EC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: EZ80L92AZ020EC00T

Table 66. GPIO Mode Selection while using the IrDA Encoder/Decoder
PS013014-0107
GPIO Port D Bits
PD0
PD1
PD2–PD7
Loopback Testing
Both internal and external loopback testing can be accomplished with the endec on the
eZ80L92 MCU. Internal loopback testing is enabled by setting the LOOP_BACK bit to 1.
During internal loopback,
IR_RXD input.
plished by transmitting data from the UART while the receiver is enabled (IR_RXEN set
to 1).
Infrared Encoder/Decoder Register
After a RESET, the infrared encoder/decoder register is set to its default value. Any Writes
to unused register bits are ignored and Reads return a value of 0. Unused bits within a reg-
ister must always be written with a value of 0. The IR_CTL register is described in
Table
Table 67. Infrared Encoder/Decoder Control Register (IR_CTL = 00BFh)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:3]
2
LOOP_BACK
Allowable GPIO
Port Mode
7
7
Any other than GPIO Mode 7
(1, 2, 3, 4, 5, 6, 8, or 9)
67.
External loopback testing of the off-chip IrDA transceiver may be accom-
000000 Reserved.
Value
0
1
IR_TXD output signal is inverted and connected on-chip to the
R/W
7
0
Internal LOOP BACK mode is disabled.
Internal LOOP BACK mode is enabled.
IR_TXD output is inverted and connected to IR_RXD input for
internal loop back testing.
Description
R/W
6
0
Alternate Function
Alternate Function
Allowable Port Mode Functions
Output, Input, Open-Drain, Open-Source,
Level-sensitive Interrupt Input, or Edge-
Triggered Interrupt Input
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
Infrared Encoder/Decoder
R/W
2
0
R/W
1
0
R/W
0
0
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