MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 76

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Clocking
21 Clocking
Figure 53
1
2
The following external clock sources are utilized on the MPC8308:
All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other
source that provides a standard CMOS square wave input.
76
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].
SYS_CLK_IN
24–66 MHz
SD_REF_CLK_B
SD_REF_CLK
125/100 MHz
System clock (SYS_CLK_IN)
Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC)
SerDes PHY clock
eSHDC clock (SD_CLK)
For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor
Reference Manual.
SD_CLK
shows the internal distribution of clocks within the device.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
+
-
eSHDC
PLL
MPC8308
Figure 53. MPC8308 Clock Subsystem
PCVTR Mux
SerDes PHY
PCI Express
Converter
Protocol
x L
ref
System
PLL
2
fb
Gen
Clk
clk tree
x M
1
e300
PLL
e300 Core
ddr_clk
eTSEC1
lbc_clk
csb_clk
DDR
/n
Clock
Divider
LBC
Clock
Divider
/2
Freescale Semiconductor
MCK[0:2]
TSEC1_TX_CLK/
TSEC1_GTX_CLK125
TSEC1_RX_CLK
MCK[0:2]
Local
Bus
Memory
Device
DDR
Memory
Device

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