MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 63

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Figure 50
Figure 51
20 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in
a moulded array process ball grid array (MAPBGA). For information on the MAPBGA, see
“Package Parameters for the MPC8308 MAPBGA,”
MPC8308 MAPBGA.”
20.1
The package parameters are as provided in the following list. The package type is 19 mm × 19 mm, 473
MAPBGA.
Freescale Semiconductor
Package outline
Interconnects
Pitch
Module height (typical)
Solder Balls
Ball diameter (typical)
Note: The clock edge is selectable on SPI.
Note: The clock edge is selectable on SPI.
Package Parameters for the MPC8308 MAPBGA
SPICLK (output)
shows the SPI timing in slave mode (external clock).
shows the SPI timing in master mode (internal clock).
Output Signals:
Output Signals:
SPICLK (input)
Input Signals:
Input Signals:
(See Note)
(See Note)
(See Note)
(See Note)
SPIMOSI
SPIMISO
SPIMISO
SPIMOSI
Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram
Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
t
NEIVKH
t
NIIVKH
t
NIKHOV
473
0.80 mm
1.39 mm
96.5 Sn/ 3.5Ag
0.40 mm
19 mm × 19 mm
t
NIIXKH
t
NEKHOV
t
NEIXKH
and
Section 20.2, “Mechanical Dimensions of the
Package and Pin Listings
Section 20.1,
63

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