EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 31
![IC WEBSERVER 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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Register Map
Table 3. Register Map
PS013014-0107
Address
(hex)
Programmable Reload Counter/Timers
0080
0081
0082
0083
0084
0085
0086
Programmable Reload Counter/Timers
0087
0088
Mnemonic
TMR0_CTL
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR2_CTL
TMR2_DR_L
TMR2_RR_L
TMR2_DR_H
TMR2_RR_H
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] =
range
not generated if the address space programmed for the I/O Chip Selects overlaps the
0080h
Registers at unused addresses within the
peripherals are not implemented. Read access to such addresses returns unpredictable
values and Write access produces no effect.
MCU.
0080h
–
00FFh
–
Name
Timer 0 Control Register
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Timer 1 Data Register—High Byte
Timer 1 Reload Register—High Byte
Timer 2 Control Register
Timer 2 Data Register—Low Byte
Timer 2 Reload Register—Low Byte
Timer 2 Data Register—High Byte
Timer 2 Reload Register—High Byte
00FFh
address range.
are routed to the on-chip peripherals. External I/O Chip Selects are
UU
). All I/O operations using 16-bit addresses within the
0080h
Table 3
–
00FFh
lists the register map for the eZ80L92
range assigned to on-chip
Reset
(hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Product Specification
Access
CPU
R/W
R/W
R/W
eZ80L92 MCU
W
W
W
W
W
W
R
R
R
R
R
R
Register Map
Page
No
82
84
85
84
86
82
84
85
84
86
82
84
85
84
86
25
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