EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 178
![IC WEBSERVER 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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- Download datasheet (3Mb)
PS013014-0107
ZDI Master Control Register
The ZDI Master Control register provides control of the eZ80L92. It is capable of forcing
a RESET and waking up the eZ80L92 from the low-power modes (HALT or SLEEP). See
Table
Table 94. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI
Register Write Address Spaces)
Bit
Position
1
ign_low_0
0
single_step
Bit
Reset
CPU Access
Note: W = Write-only.
Bit
Position
7
ZDI_RESET
[6:0]
94.
0000000 Reserved.
Value Description
Value
0
1
0
1
0
1
W
7
0
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR0 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U,
ZDI_ADDR0_H, ZDI_ADDR0_L}.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If the BRK_ADDR1 is set to 0, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
ZDI SINGLE STEP mode is disabled.
ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK
following execution of each instruction.
Description
No action.
Initiate a RESET of the eZ80L92. This bit is
automatically cleared at the end of the RESET event.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
2
0
ZiLOG Debug Interface
eZ80L92 MCU
W
1
0
W
0
0
172
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