EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 18
![IC WEBSERVER 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
52
53
54
55
56
57
58
59
60
61
62
BUSREQ
BUSACK
HALT_SLP HALT and
TMS
Symbol
NMI
V
V
RTC_XIN
RTC_XOUT Real-Time
RTC_V
V
DD
SS
SS
DD
Function
Nonmaskable
Interrupt
Bus Request
Bus
Acknowledge
SLEEP
Indicator
Power Supply
Ground
Real-Time
Clock Crystal
Input
Clock Crystal
Output
Real-Time
Clock Power
Supply
Ground
JTAG Test
Mode Select
Signal Direction
Schmitt Trigger Input,
Active Low
Input, Active Low
Output, Active Low
Output, Active Low
Input
Bidirectional
Input
The NMI input is a higher priority input
than the maskable interrupts. It is always
recognized at the end of an instruction,
regardless of the state of the interrupt
enable control bits. This input includes a
Schmitt trigger to allow RC rise times.
External devices can request the eZ80L92
MCU to release the memory interface bus
for their use, by driving this pin Low.
The eZ80L92 MCU responds to a Low on
BUSREQ, by tristating the address, data,
and control signals, and by driving the
BUSACK line Low. During bus
acknowledge cycles ADDR[23:0], IORQ,
and MREQ are inputs.
A Low on this pin indicates that the CPU
has entered either HALT or SLEEP mode
because of execution of either a HALT or
SLP instruction.
Power Supply.
Ground.
This pin is the input to the low-power
32 kHz crystal oscillator for the Real-Time
Clock.
This pin is the output from the low-power
32 kHz crystal oscillator for the Real-Time
Clock. This pin is an input when the RTC
is configured to operate from 50/60 Hz
input clock signals and the 32 kHz crystal
oscillator is disabled.
Power supply for the Real-Time Clock and
associated 32 kHz oscillator. Isolated from
the power supply to the remainder of the
chip. A battery can be connected to this
pin to supply constant power to the
Real-Time Clock and 32 kHz oscillator.
Ground.
JTAG Mode Select Input.
Description
Product Specification
Architectural Overview
12
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