EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 148
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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PS013014-0107
Clock Synchronization
slave-transmitter must release the data line to allow the master to generate a STOP or a
repeated START condition.
All masters generate their own clocks on the SCL line to transfer messages on the I
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See
High transition of this clock, however, may not change the state of the SCL line if another
clock is still within its Low period. The SCL line is held Low by the device with the long-
est Low period. Devices with shorter Low periods enter a High wait-state during this time.
When all devices concerned count off their Low period, the clock line is released and goes
High. There is no difference between the device clocks and the state of the SCL line, and
all of the devices start counting their High periods. The first device to complete its High
period again pulls the SCL line Low. In this way, a synchronized SCL clock is generated
with its Low period determined by the device with the longest clock Low period, and its
High period determined by the one with the shortest clock High period.
by Transmitter
Data Output
Data Output
from Master
by Receiver
SCL Signal
START Condition
S
Clock Pulse for Acknowledge
Figure 33. I
MSB
1
1
2
2
C Acknowledge
8
9
Product Specification
Figure
I
2
C Serial I/O Interface
34. The Low-to-
2
C interfaces
2
C bus.
142
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