EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 14
![IC WEBSERVER 20MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
21
22
23
24
25
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
Symbol
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Description
Product Specification
Architectural Overview
8
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