EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 109
![IC WEBSERVER 20MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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PS013014-0107
CLK_SEL and FREQ_SEL select the RTC clock source. If the 32 kHz crystal option is
selected the oscillator is enabled and the internal prescaler is set to divide by 32768. If the
power-line frequency option is selected, the prescale value is set by FREQ_SEL, and the
32 kHz oscillator is disabled. See
Table 51. Real Time Clock Control Register (RTC_CTRL = 00EDh)
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R = Read-only; R/W = Read/Write.
Bit
Position
7
ALARM
6
INT_EN
5
BCD_EN
4
CLK_SEL
3
FREQ_SEL
2
1
SLP_WAKE
0
RTC_UNLOCK
Value
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
R
X
7
Description
Alarm interrupt is inactive.
Alarm interrupt is active.
Interrupt on alarm condition is disabled.
Interrupt on alarm condition is enabled.
RTC count and alarm value registers are binary.
RTC count and alarm value registers are binary-coded
decimal (BCD).
RTC clock source is crystal oscillator output (32768 Hz).
On-chip 32768 Hz oscillator is enabled.
RTC clock source is power-line frequency input.
On-chip 32768 Hz oscillator is disabled.
Power-line frequency is 60 Hz.
Power-line frequency is 50 Hz.
Reserved.
RTC does not generate a Sleep-Mode Recovery reset.
RTC Alarm generates a Sleep-Mode Recovery reset.
RTC count registers are locked to prevent write access.
RTC counter is enabled.
RTC count registers are unlocked to allow write access.
RTC counter is disabled.
Table
R/W
6
0
51.
R/W
X
5
R/W
X
4
R/W
X
3
Product Specification
X
R
2
Real Time Clock
0/1
R
1
R/W
0
0
103
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