EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 108
![IC WEBSERVER 20MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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PS013014-0107
Real Time Clock Alarm Control Register
This register contains alarm enable bits for the real-time clock. The RTC_ACTRL register
is cleared by a RESET. See
Table 50. Real Time Clock Alarm Control Register (RTC_ACTRL = 00ECh)
Real-Time Clock Control Register
This register contains control and status bits for the real-time clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM flag and associated interrupt
(if INT_EN is enabled) are cleared by reading this register. The ALARM flag is updated
by clearing (locking) RTC_UNLOCK or by an increment of the RTC count. Writing to the
RTC_CTRL register also resets the RTC count prescaler allowing the RTC to be synchro-
nized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit can be checked after RESET to determine if a sleep-mode recovery is
caused by the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm
set points.
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R = Read-only; R/W = Read/Write.
Bit
Position
[7:4]
3
ADOW_EN
2
AHRS_EN
1
AMIN_EN
0
ASEC_EN
Value Description
0000
0
1
0
1
0
1
0
1
R
Table
Reserved.
The day-of-the-week alarm is disabled.
The day-of-the-week alarm is enabled.
The hours alarm is disabled.
The hours alarm is enabled.
The minutes alarm is disabled.
The minutes alarm is enabled.
The seconds alarm is disabled.
The seconds alarm is enabled.
7
0
50.
R
6
0
R
5
0
R
4
0
R/W
3
0
Product Specification
R/W
2
0
Real Time Clock
R/W
1
0
R/W
0
0
102
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