EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 120
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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PS013014-0107
Table 58. UART Interrupt Status Codes
UART FIFO Control Registers
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See
Table 59. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL =
INSTS Value
011
010
110
001
000
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:6]
TRIG
[5:3]
00D2h)
Table
Value Description
000
00
01
10
11
59.
Priority
Highest
Second
Third
Fourth
Lowest
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
Reserved.
W
7
0
Interrupt Type
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Transmit Buffer Empty
Modem Status
W
6
0
W
5
0
Universal Asynchronous Receiver/Transmitter
W
4
0
W
3
0
Product Specification
W
2
0
eZ80L92 MCU
W
1
0
W
0
0
114
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