STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 106

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

STPC® ATLAS
106/108
8a
9a
8b
9b
10
5
6
7
4
boot memory
boot memory
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
SYSRSTO#
PCI clocks
PCI cycles
Local Bus
Memory
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
Check:
clocks
cycles
cycles
HCLK
ISA
to
to
Measure HCLK is at selected frequency
25MHz < HCLK < 66MHz
Measure PCICLKO:
- maximum is 33MHz by standard
- check it is at selected frequency
- it is generated from HCLK by a division
Check PCICLKI equals PCICLKO
Measure MCLKO:
- use a low-capacitance probe
- maximum is 90MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Measure SYSRSTO# of STPC
See
Check PCI signals are toggling:
- FRAME#, IRDY#, TRDY#, DEVSEL#
- these signals are active low.
Check, with a logic analyzer, that first
PCI cycles are the expected ones:
memory read starting at address with
lower bits to 0xFFF0
Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
Check FCS0# & PRD#
Check directly on boot memory pin
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
memory less 16 bytes
The CPU fills its first cache line by fetching 16 bytes from boot memory.
(1/2, 1/3 or 1/4)
Figure 4-3
=> Minimum hardware is correctly set, CPU executes code.
Then, first instructions are executed from the CPU.
for waveforms.
How?
HCLK wire must be as short as possible
Verify PCICLKO loops to PCICLKI.
Verify maximum skew between any PCI clock
branch is below 2ns.
In Synchronous mode, check MCLKI.
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
Verify PCI slots
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
Verify HCLK speed and CPU clock mode.
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
Troubleshooting