PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 665
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 7: References for the MPEG-1 Macroblock Header Data
PNX17XX_SER_1
Preliminary data sheet
Item
Esc Count
MBA Inc
MB Type
First MB
Motion Code[0][0][0] to
Motion Code[0][1][1]
Motion Residual[0][0][0]
to Motion
Residual[0][1][1]
Start Code
CBP
Quant Scale
3.3.3 Restart the VLD Parsing
3.4 Error Handling
Default value
0
-
Undefined
0
Undefined
Undefined
-
-
-
The DCT coefficients associated with the macroblock are output to a separate
memory area. Each DCT coefficient is represented as one 32 bit quantity (16 bits of
run and 16 bits of level). For intra blocks, the DC term is expressed as 16 bits of DC
size and a 16 bit value whose most significant bits (the number of bits used for DC
level is determined by DC size) represent the DC level. Each block of DCT
coefficients is terminated by a run value of 0xff.
Run-Level Output Data
The DCT coefficients associated with the macroblock are output to a separate
memory area and each DCT coefficient is represented as one 32-bit quantity (16 bits
of run and 16 bits of level). For intra blocks, the DC term is expressed as 16 bits of
size and a 16-bit value whose most significant bits represent the DC level. The
number of bits used for DC level is determined by the DC size)‘. Each block of DCT
coefficients is terminated by a run value of 0xFF.
The restart of the parsing command at the last decoded symbol position is done
through the use of the VLD_BIT_CNT register to count the number of bits from the
main memory VLD buffer that have been consumed. The VLD_BIT_CNT register can
be initialized to zero by issuing the VLD_INIT command. It counts up when bits are
shifted out of the VLD. This counter wraps around after reaching its maximum value.
The VLD can generate two types of errors. The VLD_MC_STATUS register has two
VLD error flags.The VLD errors are 1) bitstream parsing error and 2) run-level
overflow error. See
References from IS 11172-2 document
Section 2.4.3.6
Section 2.4.3.6
Section 2.4.3.6 and Tables B-2a to B2d
Set to ‘1’ for the first macroblock of a slice
Section 2.4.2.7 and Table B-4
Section 2.4.2.7;the corresponding rsize bits are extracted from the bitstream
and stored as left justified; to get the final value shift the given number by (8 -
corresponding rsize). The rsize values are stored in MP_VLD_PI register.
Copy of the internal start-code register; see
Section 2.4.3.6 and Table B-3
Section 2.4.2.7
Rev. 1 — 17 March 2006
Table 8
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
for details on the VLD error handling procedure.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Section 5. Register
PNX17xx Series
Descriptions.
21-13
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