PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 183
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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3. Registers Definition
Table 10: Registers Summar
PNX17XX_SER_1
Preliminary data sheet
Offset
0x04,7000
0x04,7004
0x04,7008
0x04,700C
0x04,7010
0x04,7014
0x04,718
0x04,701C
0x04,7020
0x04,7024
0x04,7028
0x04,702C
0x04,7030
0x04,7034
0x04,7038-
0x04,70FC
0x04,7100
0x04,7104
0x04,7108
0x04,710C
0x04,7110
0x04,7114
0x04,7118
0x04,711C
0x04,7120
Figure 23: SPDO Clock
2.12.6 SPDO
Name
PLL0_CTL
PLL1_CTL
PLL2_CTL
PLL1_7_CTL
DDS0_CTL
DDS1_CTL
DDS2_CTL
DDS3_CTL
DDS4_CTL
DDS5_CTL
DDS6_CTL
DDS7_CTL
DDS8_CTL
CAB_DIV_PD
RESERVED
CLK_TM_CTL
CLK_MEM_CTL
CLK_2D2_CTL
CLK_PCI_CTL
CLK_MBS_CTL
CLK_TSTAMP_CTL
CLK_LAN_CTL
CLK_LAN_RX_CTL
CLK_LAN_TX_CTL
3.1 Registers Summary
DDS5
GPIO
Rev. 1 — 17 March 2006
xtal_clk
sel_clk_spdo
BLOCKING
tst_clk
Description
PLL0 Control Register
PLL1 Control Register
PLL2 Control Register
PLL 1.728 GHz Control Register
DDS0: frequency control
DDS1: frequency control
DDS2: frequency control
DDS3: frequency control
DDS4: frequency control
DDS5: frequency control
DDS6: frequency control
DDS7: frequency control
DDS8: frequency control
CAB Clocks divider powerdown signals
RESERVED
TM5250 clock control
DDR Memory clock control
2D Drawing engine clock control
PCI Clock control
MBS Clock control
Time Stamp Clock control
Ethernet Clock control
Ethernet RX Clock control
Ethernet TX Clock control
clk_spdo
slice_tst_out
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-32
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