PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 590
PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 4: Task Descriptor Opcode Table
PNX17XX_SER_1
Preliminary data sheet
Command
Jump
Exec/Stop
Queue
Load
Bits
Link to address
25:3
1:0
End of task list
2
1:0
Start processing and queue next task
25:3
1:0
Load register
31:24
19:16
11:2
1:0
2.4.2 Video Source Controls
Function
address
opcode
stop flag
opcode
address
opcode
count
mask
Index
opcode
Table 4
32 bit words; therefore, endian mode rules do apply. The command type is defined in
the lower two bits of the 32-bit word. The remaining bits are decoded depending on
the command type.
Source Video data for the MBS can be fetched via three dedicated DMA engines. It
can be fetched from memory in several packed or planar formats. The source window
is defined by one set of width and height values which are automatically translated
into the corresponding number of 64-bit words to be fetched per line for each plane.
Video lines can be fetched in a reverse order as well, thereby allowing horizontal
flipping of images for applications like video conferencing.
To allow fetching of interlaced video lines from different locations in memory, each
plane can be assigned a second set of base address registers. Pitches are defined
separately only for luma and chroma planes. The lower three bits of the first three
base address registers are used as an intra-long-word offset for the leftmost pixel
components of each line. The offset has to be a multiple of the number of bytes per
component.
Fixed Input Formats
The fixed input formats, as shown in
modes.
shows the opcodes allowed in a descriptor list. The data structure consists of
Description
Defines location where processing of commands continues.
= 00 (binary)
If this flag is set, processing of the MBS task is stopped.
= 01 (binary)
Task at this location is started after processing of current task finished.
= 10 (binary)
Define number of registers to be loaded minus one.
Write mask, if bit is zero according byte is written, if bit is set byte is not
written.
Load registers starting at offset.
= 11 (binary)
Rev. 1 — 17 March 2006
Table
5, consist of indexed, packed and planar
Chapter 19: Memory Based Scaler
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
19-7
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