KSZ8692PBI Micrel Inc, KSZ8692PBI Datasheet - Page 28

• Manufacturer Part Number: KSZ8692PBI
• Description: IC ARM9 PHY 10/100MBPS 400-PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8692PBI

• Applications: Networking & Communications
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Controller Series: KSZ
• Interface: EBI/EMI, Ethernet, I²C, I²S,PCI, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.235 V ~ 1.365 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Ram Size: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3627; KSZ8692PBI

Micrel, Inc.
March 2010
MDIO/MDC Interface
I2C/SPI Interface
PCI Interface Signals
Pin Number
H18
H17
E14
D17
D16
D15
F13
C3
D4
B2
E4
B1
SPMOSI_SDA
SPCK_SCL
Pin Name
SPI_RDY
SPMISO
PRSTN
GNT3N
GNT2N
GNT1N
SPICS
MDIO
PCLK
MDC
Pin Type
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
O
O
O
I
I
I
I
Pin Description
Clock for station management
Serial data for station management
SPI mode: master clock Output
I2C mode: serial clock output
SPI mode: master data out, slave data in
I2C mode: serial data
SPI master data in, slave data out
SPI chip select
Micrel SPI mode ready signal
PCI Reset, asserted Low
In Host Bridge Mode, the PCI Reset pin is an input. This pin as well as the
reset pin of all the devices on the PCI bus could be driven by WRSTO.
In Guest Bridge Mode, this pin is input. The system reset to drive this pin.
PCI Bus Clock input.
This signal provides the timing for the PCI bus transactions. This signal is used to
drive the PCI bus interface and the internal PCI logic. All PCI bus signals are sampled
on the rising edges of the PCLK. PCLK can operate from 20MHz to 33MHz, or
66MHz.
PCI Bus Grant 3
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ3N.
In Guest Bridge Mode, this is unused.
PCI Bus Grant 2
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ2N.
In Guest Bridge Mode, this is unused.
PCI Bus Grant 1
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ1N.
In Guest Bridge Mode, this is an output signal to indicate to the
external PCI bus arbiter that KSZ8692PB is requesting access to the
PCI bus.
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M9999-031810-4.0
KSZ8692PB