KSZ8692PBI Micrel Inc, KSZ8692PBI Datasheet
KSZ8692PBI
Specifications of KSZ8692PBI
KSZ8692PBI
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KSZ8692PBI Summary of contents
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... Integrated PCI Arbiter supports three external masters • Configurable as Host bridge or Guest device • Glueless Support for mini-PCI or CardBus devices Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( March 2010 KSZ8692PB Integrated Networking and Communications Controller Rev ...
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Micrel, Inc. Block Diagram March 2010 Figure 1. KSZ8692PB Block Diagram 2 KSZ8692PB M9999-031810-4.0 ...
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... DDR Data Width Changed to 16-bit 4.0 01/28/10 DDR Data Width Changed to 32-bit March 2010 Ordering Information Temp. Part Number Range KSZ8692PB 0°C to 70°C KSZ8692PBI -40°C to 85°C 3 KSZ8692PB Lead Package Finish 400-Pin PBGA Pb-Free 400-Pin PBGA Pb-Free M9999-031810-4.0 ...
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Micrel, Inc. Contents System Level Applications ...................................................................................................................................................... 6 Functional Description............................................................................................................................................................. 7 ARM High-Performance Processor .................................................................................................................................... 8 FLASH/ROM/SRAM Memory and External I/O Interface ................................................................................................... 8 NAND Flash Memory Interface......................................................................................................................................... 10 DDR Controller.................................................................................................................................................................. 11 SDIO/SD Host Controller .................................................................................................................................................. 15 IP Security Engine ...
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Micrel, Inc. List of Figures Figure 1. KSZ8692PB Block Diagram..................................................................................................................................... 2 Figure 2. Peripheral Options and Examples ........................................................................................................................... 6 Figure 3. KSZ8692PB Functional Block Diagram ................................................................................................................... 7 Figure 4. Static Memory Interface Examples .......................................................................................................................... 9 Figure 5. External I/O Interface ...
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Micrel, Inc. System Level Applications March 2010 Figure 2. Peripheral Options and Examples 6 KSZ8692PB M9999-031810-4.0 ...
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Micrel, Inc. Functional Description The KSZ8692PB is a highly-integrated embedded application controller that is designed to provide a single-chip solution for a wide range of applications that require network security, high-speed networking, multiple I/O controllers and interface to standard peripherals. ...
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Micrel, Inc. ARM High-Performance Processor The KSZ8692PB is built around the 16/32-bit ARM922T RISC processor designed by Advanced RISC Machines. The ARM922T is a scalable, high-performance processor that was developed for highly integrated SoC applications. Its simple, elegant, and fully ...
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Micrel, Inc. March 2010 Figure 4. Static Memory Interface Examples Figure 5. External I/O Interface Examples 9 KSZ8692PB M9999-031810-4.0 ...
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Micrel, Inc. NAND Flash Memory Interface The KSZ8692PB NAND controller provides interface to external NAND Flash memory. A total of two banks are supported. NAND Flash bank0 can be configured by power-up strap option to operate as boot bank. Both ...
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Micrel, Inc. DDR Controller The KSZ8692PB DDR memory controller provides interface for accessing external Double Data Rate Synchronous DRAM. In addition the KSZ8692PB provides two integrated DDR differential clock drivers for a complete glueless DDR interface solution. • ...
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Micrel, Inc. A dedicated internal PLL provides clocking to the DDR memory controller and the two differential clock drivers. This PLL is programmable up to 200MHz and independent of AHB and ARM processor core clocks. Figures 8 and 9 illustrate ...
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Micrel, Inc. Figure 9. Four8-bit DDR Memory Devices Interface Example March 2010 13 KSZ8692PB M9999-031810-4.0 ...
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Micrel, Inc. DDR memory controller access to memory bank is typically of burst type. Figures 10 and 11 are examples of burst read and write cycles. March 2010 Figure 10. Burst DDR Read Timing Figure 11. Burst DDR Write Timing ...
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Micrel, Inc. SDIO/SD Host Controller Integrated SDIO/SD host controller provides interface for removable mass storage memory card and I/O devices. • Meets SD Host Controller Standard Specification Version 1.0 • Meets SD memory card spec 1.01, MMC spec 3.31 • ...
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Micrel, Inc. USB 2.0 Interface Integrated dual USB 2.0 interface can be configured as 2-port host, or host + device. Figures 12 and 13 illustrate examples of USB 2.0 interface applications. • Compliant with USB Specification Revision 2.0 • Compliant ...
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Micrel, Inc. PCI Interface The KSZ8692PB integrates a PCI to AHB bridge solution for interfacing with 32-bit PCI, including miniPCI, and cardbus devices where it’s common for 802.11x-based Wireless products. The PCI-AHB bridge supports two modes of operation in the ...
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Micrel, Inc. A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state. A wake-up signal is caused by: 1. Detection of a change in the network link ...
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Micrel, Inc. If the network controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8692PB controller detects the data sequence, however, it then alerts the ...
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Micrel, Inc. I2C The I2C interface is a 2-pin (SCL & SDA) generic serial bus interface for both control and data. The KSZ8692PB supports master mode I2C interface. To increase the firmware efficiency, KSZ8692PB is equipped with hardware assisted logic ...
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Micrel, Inc. System Level Interfaces The following figures illustrate the high-level system connections to the KSZ8692PB. Note these figures are for illustration purpose only. The system designer must refer to Evaluation Design Kit for actual circuit implementation. According to some ...
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Micrel, Inc. Signal Descriptions by Group Pin Number Pin Name System Interface R5 RESETN N5 WRSTO W1 XCLK2 Y1 XCLK1 H19 CLK25MHz Y15, Y14 DDCLKO[1:0] W15, W14 DDCLKON[1:0] U13 SDCLKEO T7, U7 VREF W3 SDOCLK Y3 SDICLK Y17, Y16 DDCLKO[3:2] ...
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Micrel, Inc. Pin Number Pin Name L3 ECS2 N1 ECS1 M2 ECS0 K3 RCSN1 L1 RCSN0 N2 EWAITN M1 EROEN (WRSTPLS) J5 ERWEN1 J4 ERWEN0 R3 NCLE U2 NALE T3 NCEN1 V3 NCEN0 R4 NREN T4 NWEN U3 NWPN P4, ...
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Micrel, Inc. Pin Number Pin Name DDR Interface T17, V18, DADDR[13..0] U17, T16, W20, W19, Y20, Y19, W18, V17, U16, T15, Y18, V16 V13, U11, DDATA[31..0] V12, W13, Y13, W12, V11, U10, V10, Y11, W10, U9, Y10, V9, W9, Y9, ...
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Micrel, Inc. Pin Number Pin Name Ethernet Port 0 M16 P0_RXC P18, N17, P0_RXD[3:0] P17, N16 N18 P0_RXDV P19 P0_RXER M17 P0_CRS P20 P0_COL M18 P0_TXC L17, M19, P0_TXD[3:0] N20, N19 L16 P0_TXEN Ethernet Port 1 K19 P1_RXC L20, L19, ...
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Micrel, Inc. Pin Number Pin Name USB Interface G19 U1P I/O (analog) G20 U1M I/O (analog) F19 U2P I/O (analog) F20 U2M I/O (analog) G17 USBXI G18 USBXO O (analog) H16 USBREXT G16 USBTEST O (Analog) G15 USBCFG F18 USBHOVC0 ...
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Micrel, Inc. Pin Number Pin Name General Purpose I/O B14 SLED/GPIO[19] B15 CPUINTN/ GPIO[18] B16, B17, GPIO[17:12] B18, D18, E15, D19 F14 UART 4 RTSN /GPIO[11] E16 UART 4 CTSN /GPIO[10] E17 UART 3 RTSN /GPIO[9] E19 UART 3 CTSN ...
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Micrel, Inc. Pin Number Pin Name Pin Type MDIO/MDC Interface H18 MDC H17 MDIO I2C/SPI Interface E14 SPCK_SCL D17 SPMOSI_SDA D16 SPMISO D15 SPICS F13 SPI_RDY PCI Interface Signals C3 PRSTN B2 PCLK E4 GNT3N D4 GNT2N B1 GNT1N March ...
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Micrel, Inc. Pin Number Pin Name Pin Type PCI Interface Signals D3 REQ3N E6 REQ2N C1 REQ1N B3, E7, D6, PAD[31..0] A2, B4, A3, D7, C5, C6, B5, A4, A5, B6, E8, C7, D8, D10, B10, A11, B11, C11, A12, ...
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Micrel, Inc. Pin Number Pin Name PCI Interface Signals E9 TRDYN A9 DEVSELN B7 IDSEL B9 STOPN A10 PERRN C9 SERRN (open drain) C4 M66EN F6 PCLKOUT3 D1 PCLKOUT2 D2 PCLKOUT1 E5 PCLKOUT0 March 2010 Pin Type Pin Description I/O ...
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Micrel, Inc. Pin Number Pin Name PCI Interface Signals A8 CLKRUNN C2 MPCIACTN D5 PBMS A1 PMEN UART Signals P16 U1RXD R16 U1TXD O (Tri-State) R19 U1CTSN R20 U1DCDN P15 U1DSRN R15 U2RXD R17 U2TXD O (Tri-State) R18 U3RXD N15 ...
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Micrel, Inc. Pin Number Pin Name Test Signals P5 SCANEN V2 TESTEN V1 TESTEN1 Y2 TEST1 O (analog) W2 TEST2 O (analog) Power and Ground (96) N6, M6, M7, VDD1.2 G7, G8, G9, M14, M15, N14, P11, P12,P13,P14 G6, H6, ...
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Micrel, Inc. Pin Number Pin Name Power and Ground (96) G13 USBCVDDA3.3 G14 USB2VDDA3.3 H13, J13, USBVSSA3.3 K13 J15 USB1VDD1.2 H15 USB2VDD1.2 J12 USBVSS1 H12 USBVSS2 Notes Power supply Input Output. O/I = ...
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Micrel, Inc. Power-Up Strapping Options Certain pins are sampled upon power up or reset to initialize KSZ8692PB system registers per system configuration requirements. Pin Number Pin Name Pin Type E3 SADDR[0] E1, E2 SADDR[2:1] F4 SADDR[3] F5 SADDR[4] F3 SADDR[5] ...
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Micrel, Inc. Pin Number Pin Name Pin Type M1 EROEN Ipd/O (WRSTPLS) J4 ERWEN0 Ipd/O R3 NCLE Ipd/O U2 NALE Ipd/O March 2010 Pin Description ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low. When asserted, this signal controls the output enable ...
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Micrel, Inc. Pin Number Pin Name Pin Type T4 NWEN U3 NWPN G15 USBCFG Test Pins Strapping Options Pin Number Pin Name Pin Type P5 SCANEN V2 TESTEN V1 TESTEN1 Notes Power supply Input. O ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage (V 1.2, PLLDV 1.2, PLLSV USB1V 1.2, USB2V 1.2 ) ..................–0.5V to +1. 2.5…… ......……… …………………..–0.5V to +3. 3.3, PLLV A3.3, PLLDV ...
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Micrel, Inc. Timing Specifications Figure 16 provides power sequencing requirement with respect to system reset. Note: Power sequencing of supply voltages must be in order of 3.3V first, 2.5V/2.6V next and 1.3V last Symbol Parameter t Stable supply voltages to ...
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Micrel, Inc. (1) Symbol Parameter RBiTACC Programmable bank i access time RBiTPA Programmable bank i page access time Table 2. Programmable Static Memory Timing Parameters Note: 1. "i" Refers to chip select parameters 0 and 1. Figure 19 provides external ...
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Micrel, Inc. Symbol Parameter T Valid address to CS setup time cta T OE valid to CS setup time cos T Valid read data to OE setup time dsu T WE valid to CS setup time cws T Write data ...
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Micrel, Inc. Signal Location Information PMEN PAD28 PAD26 PAD21 PAD20 B GNT1N PCLK PAD31 PAD27 PAD22 MPCIACT C REQ1N N PRSTN M66EN PAD24 PCLKOUT PCLKOUT REQ3N GNT2N PMBS PCLKOUT E SADDR2 ...
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Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, ...