KSZ8692PBI Micrel Inc, KSZ8692PBI Datasheet - Page 17

• Manufacturer Part Number: KSZ8692PBI
• Description: IC ARM9 PHY 10/100MBPS 400-PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8692PBI

• Applications: Networking & Communications
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Controller Series: KSZ
• Interface: EBI/EMI, Ethernet, I²C, I²S,PCI, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.235 V ~ 1.365 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Ram Size: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3627; KSZ8692PBI

PCI Interface
The KSZ8692PB integrates a PCI to AHB bridge solution for interfacing with 32-bit PCI, including miniPCI, and cardbus
devices where it’s common for 802.11x-based Wireless products. The PCI-AHB bridge supports two modes of operation
in the PCI bus environment: host bridge mode and guest bridge mode. In the host bridge mode, the ARM processor acts
as the host of the entire system. It configures other PCI devices and coordinates their transactions, including initiating
transactions between the PCI devices and AHB bus subsystem. An on-chip PCI arbiter is included to determine the PCI
bus ownership among up to three PCI master devices.
In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the local
ARM host processor through the AHB bus and the KSZ8692PB can be configured by either the ARM or the PCI host
CPU. In guest bridge mode, the on-chip PCI arbiter is disabled. In both cases, the KSZ8692PB memory subsystem is
accessible from either the PCI host or the ARM processor. Communications between the external host CPU and the ARM
processor is accomplished through message passing or through shared memory.
• Compliant to PCI revision 2.3
• Support 33 and 66MHz, 32-bit data PCI bus
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• AHB bus and PCI bus operate at independent clock domains
• Supports big endian and little endian on AHB
• PCI bus Round Robin arbiter for three external masters
• Supports high speed bus request and bus parking
• Dedicated DMA channel for bulk data transfer to/from DDR memory
Ethernet MAC Ports (Port 0 = WAN, Port 1 = LAN)
The KSZ8692PB integrates two Ethernet controllers that operate at 10 and 100 Mbps. Each controller has an interface
that operates as MII to an external 10/100 PHY to complete Ethernet network connectivity. An integrated 25 MHz clock
eliminates external crystal or oscillator requirement for PHY to reduce cost. Integrated 2-pin (MDC & MDIO) Station
Manager allows ARM processor to access PHY registers and pass control and status parameters. Wake-on-LAN is
supported as part of the power management mechanism. Each port has a dedicated MIB counter to accumulate statistics
for received and transmitted traffic.
• IEEE 802.3 compliant MAC layer function
• MII interface compliant to Clause 22.2.4.5 of the IEEE 802.3u Specification
• 10/100 Mbps half and full-duplex operation
• Automatic CRC generation and checking
• Automatic error packet discard
• Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum generation to offload host CPU
• Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum error detection
• Supports 32 rules ACL filtering
• Maximum frame length support is 2000 Byte at WAN port and 9K-byte at LAN port
• Contains large independent receive and transmit FIFOs (8KB receive / 8KB transmit at WAN and 24KB receive / 22KB
• Data alignment logic and scatter gather capability
• Configurable as MAC or PHY mode
• Separate transmit and receive DMA channels for each port
Wake-on-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is
pre-programmed by the policy owner or other software with information on how to identify wake frames from other network
traffic.
Micrel, Inc.
March 2010
Support 32-bit miniPCI or cardbus devices
Supports both regular and memory-mapped I/O on the PCI interface
transmit at LAN) for back-to-back packet receive, and guaranteed no-under run packet transmit
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M9999-031810-4.0
KSZ8692PB