PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 489

• Manufacturer Part Number: PNX1502E/G,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1298; 935277748557; PNX1502E/G

NXP Semiconductors
Volume 1 of 1
2. Functional Description
Table 1: Module signal pins
PNX15XX_PNX952X_SER_N_4
Product data sheet
Signal
clk_fgpi
fgpi_d_valid
fgpi_start
or
fgpi_rec_start
fgpi_stop
or
fgpi_buf_start
fgpi_data
fgpi_interrupt
fgpi_intr_active
fgpi_clk_pol
fgpi_resetn
Type
input
input
input
input
input
output
output
output
output
2.1 Reset
Description
From Clock Module. External FGPI clock on VDI_C2 pin is connected to the Clock Module.
FGPI data and control signals are sampled at each rising edge on clk_fgpi when fgpi_d_valid
is asserted high. Use the PNX15xx/952x Series Clock Module to change clk_fgpi
characteristics.
From External PAD, VDI_V2 via Input Router.
In all operating modes fgpi_d_valid is used to qualify data & control signals. fgpi_start
(fgpi_rec_start), fgpi_stop (fgpi_buf_start), and fgpi_data will only be sampled when
fgpi_d_valid is high during the rising edge of clk_fgpi.
From External PAD, VDI_D[32] via Input Router.
Message Passing Mode:
A programmable transition on fgpi_start (see FGPI_CTL register bits 3:2) indicates the start of
a message. The message starts on the clk_fgpi edge when the transition was detected.
Record Capture Mode:
A programmable transition on fgpi_rec_start (see FGPI_CTL register bits 3:2) indicates the
start of a record. The record starts on the clk_fgpi edge when the transition was detected.
From External PAD, VDI_D[33] via Input Router.
Message Passing Mode:
A programmable transition on fgpi_stop (see FGPI_CTL register bits 7:5) indicates the end of
a message. The message ends on the clk_fgpi edge when the transition was detected.
Record Capture Mode:
A programmable transition on fgpi_buf_start (see FGPI_CTL register bits 7:5) indicates the
start of a new buffer. The new buffer starts on the clk_fgpi edge when the transition was
detected.
From External PAD’s, VDI_D[31:0] via Input Router.
General Purpose high speed data input sampled on the rising edge of clk_fgpi when
fgpi_d_valid is high.
Interrupt status connects to the TriMedia Processor in the PNX15xx/952x Series.
Not used in the PNX15xx/952x Series.
Not used in the PNX15xx/952x Series.
Goes to the PNX15xx/952x Series Input Router module to reset it’s registers used in routing
data to the FGPI module.
FGPI is reset by any PNX15xx/952x Series system reset or by setting the
SOFTWARE_RESET bit in the FGPI_SOFT_RST register.
Rev. 4.0 — 03 December 2007
Chapter 14: FGPI: Fast General Purpose Interface
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
14-489