PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 348

• Manufacturer Part Number: PNX1502E/G,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1298; 935277748557; PNX1502E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 3:
Power Sequencing State Machine Block Diagram
3.2.1 IDLE state
3.2.2 DCEN state
BLEN
calculated using a 26-bit counter that is controlled by the state machine. This counter
runs on the 27 MHz clock (the input PNX15xx/952x Series crystal). The state
machine is shown in
After reset, the state machine comes up in the IDLE state. In this state, when the
lcd_enbl signal (which is asserted when both lcd_if_en and start_pud_seq bits are
set) is asserted, the power up sequence is started by asserting the TFTVDDON
signal and loading the counter with PWREN_DCE_DELAY that is set in the
LCD_SETUP register. The counter starts to count down after it is loaded.
If the lcd_enbl is de-asserted in the IDLE state, then the state machine goes to the
PEPED state, de-asserts the TFTVDDON signal and loads the counter with
PWR_EN_PWREN_DELAY value.
If the lcd_enbl is still asserted when the counter decrements to zero, then the state
machine goes to DCEN state and asserts the ‘dce’ signal. It also loads the counter
with DCE_BKLT_DELAY value.
In the DCEN state, when the counter reaches zero and lcd_enbl is still asserted, then
the state machine transitions to the BLEN state and asserts the TFTBKLTON signal.
This completes the power up sequence.
If the lcd_enbl signal is de-asserted when ‘dce’ signal is still asserted, then the ‘dce’
signal is de-asserted and the counter is loaded with DCE_PWREN_DELAY value.
There is no state transition.
If the counter reaches zero with both the dce and lcd_enbl signal de-asserted, the
state machine transitions to the PEPED state. During this transition, the TFTVDDON
signal is de-asserted and the counter is loaded with PWREN_PWREN_DELAY value.
!lcd_enbl && cnt_done
lcd_enbl && cnt_done
Rev. 4.0 — 03 December 2007
DCEN
Figure
3.
!lcd_enbl && cnt_done && !dce
IDLE
cnt_done
lcd_enbl_neg
PNX15xx/952x Series
PEPED
Chapter 10: LCD Controller
© NXP B.V. 2007. All rights reserved.
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