XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 83

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
September 18, 1996 (Version 1.04)
Write Operation
Address write cycle time
Clock K pulse width
Address setup time
Address hold time
DIN setup time
DIN hold time
WE setup time
WE hold time
Data valid
after clock K
before clock K
(clock K period)
(active edge)
before clock K
after clock K
before clock K
after clock K
after clock K
Description
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Speed Grade
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
DATA OUT
Size
ADDRESS
WCLK (K)
DATA IN
WE
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
WCTS
WPTS
WSTS
WHTS
WOTS
DHTS
ASTS
AHTS
DSTS
WOS
WCS
WPS
WSS
WHS
AHS
DSS
DHS
ASS
15.0
15.0
Min
7.5
7.5
2.8
2.8
3.5
2.5
2.2
2.2
0
0
0
0
0
0
T
ILO
-4
T
T
T
WSS
1 ms
1 ms
DSS
ASS
Max
10.3
11.6
OLD
14.4
14.4
Min
7.2
7.2
2.4
2.4
3.2
1.9
2.0
2.0
T
0
0
0
0
0
0
T
WOS
T
T
DHS
WHS
AHS
-3
T
1 ms
1 ms
10.3
WPS
Max
8.8
NEW
T
ILO
X6461
11.6
11.6
Min
5.8
5.8
2.0
2.0
2.7
1.7
1.6
1.6
Preliminary
0
0
0
0
0
0
-2
1 ms
1 ms
Max
7.9
9.3
4-87