XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 13

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in
Figure 6
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
September 18, 1996 (Version 1.04)
Figure 6: XC4000-Series Dual-Port RAM, Simple
Model
DPRA[3:0]
WCLK
A[3:0]
WE
D
shows a simple model of an XC4000-Series CLB
Figure
RAM16X1D Primitive
5.
G Function Generator
F Function Generator
WE
D
AR[3:0]
AW[3:0]
WE
D
AR[3:0]
AW[3:0]
D
D
Q
Q
DPO (Dual Port Out)
Registered DPO
SPO (Single Port Out)
Registered SPO
X6755
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table
ured in this mode.
Note: The pulse following the active edge of WCLK (T
in
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Table 8: Dual-Port Edge-Triggered RAM Signals
D
A[3:0]
DPRA[3:0]
WE
WCLK
SPO
DPO
RAM Signal
Figure
8. See
5) must be less than one millisecond wide. For
Figure 7
D0
F1-F4
G1-G4
WE
K
F’
G’
CLB Pin
for a block diagram of a CLB config-
Data In
Read Address for F,
Write Address for F and G
Read Address for G
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by
DPRA[3:0])
Function
4-17
WPS