XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 36
XC4010L-5PQ208C
Manufacturer Part Number
XC4010L-5PQ208C
Description
IC 3.3V FPGA 400 CLB'S 208-PQFP
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet
1.XC4005L-5PC84C.pdf
(175 pages)
Specifications of XC4010L-5PQ208C
Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
160
Number Of Gates
10000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1124
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XC4000 Series Field Programmable Gate Arrays
Octal I/O Routing (XC4000EX only)
Between the XC4000EX CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buff-
ers are staggered, so each line goes through a buffer at
every eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
4-40
Figure 34: XC4000EX Octal I/O Routing
IOB
IOB
IOB
IOB
Figure
34.)
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure
IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Segment with nearest buffer
connects to segment with furthest buffer
34.
September 18, 1996 (Version 1.04)
IOB
IOB
IOB
IOB
X6607
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