XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 23

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

ment, but whichever one is used should be the same clock
as the related internal logic. Since the FastCLK pads are
different from the Global Early and Global Low-Skew pads,
care must be taken to ensure that skew external to the
device does not create internal timing difficulties.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele-
ment, and the inverter is absorbed into the IOB. If a single
BUFG output is used to drive both clock inputs, the soft-
ware automatically runs the clock through both a Global
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately.
Figure 17 on page 25
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEDDELAY to ensure a zero hold time. This
default can be overridden to remove the delay, if FastClk is
used, by attaching a NODELAY attribute or property to the
ILFFX or ILFLX latch. Select the desired delay based on
the discussion in the previous subsection.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and can pass directly to the pad or be stored in an edge-
triggered flip-flop. The functionality of this flip-flop is shown
in
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently
configured for each IOB.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected exter-
nally to sink up to 24 mA. (XC4000L and XC4000XL out-
puts can sink up to 4 mA, and two adjacent XC4000L and
XC4000XL outputs can sink up to 8 mA.) The XC4000E
and XC4000EX FPGAs can thus directly drive buses on a
printed circuit board.
September 18, 1996 (Version 1.04)
Table
13.
also shows a two-tap delay on the
Table 13: Output Flip-Flop Functionality (active rising
edge is shown)
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-
up transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally con-
figured as CMOS drivers, with p-channel pull-up transistors
pulling to Vcc. This MakeBits option applies to all outputs
on the device. It is not individually programmable.
Outputs of low-voltage devices must be configured as
CMOS at all times. They can drive the inputs of any 5-Volt
device with TTL-compatible thresholds.
Any XC4000-Series 5-Volt device with its outputs config-
ured in TTL mode can drive the inputs of any typical 3.3-
Volt device. (For a detailed discussion of how to interface
between 5 V and 3.3 V devices, see the 3V Products sec-
tion of The Programmable Logic Data Book .)
Supported destinations for XC4000-Series device outputs
are shown in
Table 14: Supported Destinations for XC4000-Series
Outputs
Power-Up
or GSR
Flip-Flop
Legend:
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs
Any device, Vcc = 5 V,
TTL-threshold inputs
Any device, Vcc = 5 V,
CMOS-threshold inputs
Mode
__/
SR
0*
1*
X
Z
1. Only if destination device has 5-V tolerant inputs
Destination
Table
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Clock
__/
X
X
X
0
14.
Enable
Clock
1*
X
X
X
0
CMOS
3.3 V,
Unreliable
0*
0*
0*
0*
XC4000-Series
T
1
Data
Outputs
TTL
5 V,
D
X
X
D
X
X
CMOS
some
5 V,
SR
Q
Q
Q
D
Z
4-27
1