XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 68

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
4-72
Figure 59: Synchronous Peripheral Mode Circuit Diagram
CONTROL
SIGNALS
DATA BUS
PROGRAM
CLOCK
4.7 k
4.7 k
8
V
CC
RDY/BUSY
INIT
D
PROGRAM
CCLK
0-7
PERIPHERAL
M0 M1
XC4000E/EX
SYNCHRO-
N/C
NOUS
DONE
DOUT
M2
NOTE:
M2 can be shorted to Ground
if not used as I/O
4.7 k
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisy-
chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
OPTIONAL
DAISY-CHAINED
FPGAs
INIT
CCLK
DIN
PROGRAM
September 18, 1996 (Version 1.04)
M0 M1
XC4000E/EX
SLAVE
N/C
DONE
DOUT
M2
X5996