XC5VLX220-1FFG1760C Xilinx Inc, XC5VLX220-1FFG1760C Datasheet - Page 33

• Manufacturer Part Number: XC5VLX220-1FFG1760C
• Description: IC FPGA VIRTEX-5 220K 1760FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FFG1760C

• Total Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Figure 1-7
X-Ref Target - Figure 1-7
BUFGMUX and BUFGMUX_1
BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This
primitive is based on BUFGCTRL with some pins connected to logic High or Low.
Figure 1-8
available for BUFGMUX and BUFGCTRL.
X-Ref Target - Figure 1-8
Since the BUFGMUX uses the CE pins as select pins, when using the select, the setup time
requirement must be met. Violating this setup time might result in a glitch.
Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL.
Figure 1-9
BUFGCE_1(CE)
BUFGCE_1(O)
illustrates the timing diagram for BUFGCE_1.
illustrates the relationship of BUFGMUX and BUFGCTRL. A LOC constraint is
illustrates the timing diagram for BUFGMUX.
BUFGCE_1(I)
I1
I0
S
BUFGMUX
Figure 1-7: BUFGCE_1 Timing Diagram
Figure 1-8: BUFGMUX as BUFGCTRL
www.xilinx.com
O
T
BCCKO_O
S
GND
GND
V
V
T
DD
DD
BCCCK_CE
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
ug190_1_08_032206
ug190_1_07_032206
O
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